diff --git a/CI/utils/stm32wrapper.py b/CI/utils/stm32wrapper.py index 25f4a3dad8..ccde5797e4 100644 --- a/CI/utils/stm32wrapper.py +++ b/CI/utils/stm32wrapper.py @@ -131,9 +131,9 @@ def printCMSISStartup(log): # File name fn = os.path.basename(fp) valueline = re.split("_|\\.", fn) - upper = ( - valueline[1].upper().replace("X", "x").replace("MP15xx", "MP1xx") - ) + if "stm32mp15" in valueline[1] and not valueline[1].endswith("xx"): + valueline[1] += "xx" + upper = valueline[1].upper().replace("X", "x") out_file.write( """ #elif defined({}) #define CMSIS_STARTUP_FILE \"{}\" diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 95db9ec4b2..b6271acfeb 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -378,7 +378,19 @@ #define CMSIS_STARTUP_FILE "startup_stm32l4s7xx.s" #elif defined(STM32L4S9xx) #define CMSIS_STARTUP_FILE "startup_stm32l4s9xx.s" - #elif defined(STM32MP1xx) + #elif defined(STM32MP151Axx) + #define CMSIS_STARTUP_FILE "startup_stm32mp151a_cm4 .s" + #elif defined(STM32MP151Cxx) + #define CMSIS_STARTUP_FILE "startup_stm32mp151c_cm4.s" + #elif defined(STM32MP153Axx) + #define CMSIS_STARTUP_FILE "startup_stm32mp153a_cm4.s" + #elif defined(STM32MP153Cxx) + #define CMSIS_STARTUP_FILE "startup_stm32mp153c_cm4.s" + #elif defined(STM32MP157Axx) + #define CMSIS_STARTUP_FILE "startup_stm32mp157a_cm4.s" + #elif defined(STM32MP157Cxx) + #define CMSIS_STARTUP_FILE "startup_stm32mp157c_cm4.s" + #elif defined(STM32MP15xx) #define CMSIS_STARTUP_FILE "startup_stm32mp15xx.s" #elif defined(STM32WB30xx) #define CMSIS_STARTUP_FILE "startup_stm32wb30xx_cm4.s" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c index 19419bec05..b21bfa5ec4 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c @@ -34,6 +34,9 @@ #ifdef STM32L4xx #include "stm32l4xx_hal_smartcard.c" #endif +#ifdef STM32MP1xx + #include "stm32mp1xx_hal_smartcard.c" +#endif #ifdef STM32WBxx #include "stm32wbxx_hal_smartcard.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c index a123ae83cd..0487879b56 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c @@ -22,6 +22,9 @@ #ifdef STM32L4xx #include "stm32l4xx_hal_smartcard_ex.c" #endif +#ifdef STM32MP1xx + #include "stm32mp1xx_hal_smartcard_ex.c" +#endif #ifdef STM32WBxx #include "stm32wbxx_hal_smartcard_ex.c" #endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h index 9599588563..47735188b5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; @@ -430,6 +429,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1020,18 +1237,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1193,110 +1410,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1375,10 +1488,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1708,7 +1845,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1770,36 +1907,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1865,7 +2002,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -1965,7 +2101,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2556,20 +2692,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2578,69 +2714,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2656,42 +2806,42 @@ typedef struct #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2700,71 +2850,72 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2802,6 +2953,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2828,7 +2980,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3008,6 +3159,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3028,7 +3180,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3077,7 +3228,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3086,7 +3238,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3454,7 +3606,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3682,6 +3833,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -3955,7 +4107,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4226,7 +4378,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4263,7 +4415,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4300,7 +4452,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4337,7 +4489,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4712,6 +4864,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -5598,6 +5841,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -16656,6 +21464,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -17337,7 +22146,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -18218,766 +23027,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -18994,85 +25370,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -19091,1912 +25492,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -21179,7 +28521,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -21793,42 +29134,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21852,78 +29193,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -28906,7 +36290,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -28952,10 +36336,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -29004,7 +36388,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h index b97c7a74ec..2d8f9d671b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; @@ -396,6 +395,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -986,18 +1203,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1159,110 +1376,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1341,10 +1454,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1674,7 +1811,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1736,36 +1873,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1831,7 +1968,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -1931,7 +2067,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2522,20 +2658,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2544,69 +2680,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2622,42 +2772,42 @@ typedef struct #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2666,71 +2816,72 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2768,6 +2919,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2794,7 +2946,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -2974,6 +3125,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -2994,7 +3146,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3043,7 +3194,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3052,7 +3204,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3420,7 +3572,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3648,6 +3799,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -3921,7 +4073,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4192,7 +4344,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4229,7 +4381,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4266,7 +4418,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4303,7 +4455,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4678,6 +4830,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -5564,6 +5807,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -16622,6 +21430,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -17303,7 +22112,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -18184,766 +22993,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -18960,85 +25336,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -19057,1912 +25458,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -21145,7 +28487,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -21759,42 +29100,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21818,78 +29159,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -28872,7 +36256,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -28918,10 +36302,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -28970,7 +36354,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h index daa83a5637..c5b43ad73b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; @@ -430,6 +429,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1020,18 +1237,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1193,110 +1410,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1375,10 +1488,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1708,7 +1845,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1770,36 +1907,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1865,7 +2002,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -1965,7 +2101,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2604,20 +2740,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2626,69 +2762,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2704,43 +2854,43 @@ typedef struct #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2749,72 +2899,73 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2852,6 +3003,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2878,7 +3030,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3060,6 +3211,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3080,7 +3232,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3129,7 +3280,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3138,7 +3290,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3506,7 +3658,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3734,6 +3885,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4007,7 +4159,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4278,7 +4430,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4315,7 +4467,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4352,7 +4504,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4389,7 +4541,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4764,6 +4916,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -5795,6 +6038,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -16853,6 +21661,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -17534,7 +22343,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -18415,766 +23224,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -19191,85 +25567,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -19288,1924 +25689,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -21388,7 +28718,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -22002,42 +29331,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -22061,78 +29390,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -29115,7 +36487,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -29161,13 +36533,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -29215,7 +36587,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h index 203bc4ddab..d914421590 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; @@ -396,6 +395,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -986,18 +1203,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1159,110 +1376,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1341,10 +1454,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1674,7 +1811,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1736,36 +1873,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1831,7 +1968,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -1931,7 +2067,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2570,20 +2706,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2592,69 +2728,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2670,43 +2820,43 @@ typedef struct #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2715,72 +2865,73 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2818,6 +2969,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2844,7 +2996,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3026,6 +3177,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3046,7 +3198,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3095,7 +3246,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3104,7 +3256,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3472,7 +3624,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3700,6 +3851,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -3973,7 +4125,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4244,7 +4396,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4281,7 +4433,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4318,7 +4470,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4355,7 +4507,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4730,6 +4882,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -5761,6 +6004,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -16819,6 +21627,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -17500,7 +22309,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -18381,766 +23190,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -19157,85 +25533,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -19254,1924 +25655,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -21354,7 +28684,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -21968,42 +29297,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -22027,78 +29356,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -29081,7 +36453,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -29127,13 +36499,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -29181,7 +36553,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h index 49f3c79c57..fd0afa7ea2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; @@ -430,6 +429,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1020,18 +1237,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1193,110 +1410,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1375,10 +1488,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1708,7 +1845,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1770,36 +1907,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1865,7 +2002,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -1965,7 +2101,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2556,20 +2692,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2578,69 +2714,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2656,42 +2806,42 @@ typedef struct #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2700,71 +2850,72 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2802,6 +2953,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2828,7 +2980,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3008,6 +3159,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3028,7 +3180,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3077,7 +3228,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3086,7 +3238,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3454,7 +3606,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3682,6 +3833,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -3955,7 +4107,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4226,7 +4378,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4263,7 +4415,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4300,7 +4452,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4337,7 +4489,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4712,6 +4864,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -5598,6 +5841,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -16656,6 +21464,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -17337,7 +22146,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -18218,766 +23027,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -18994,85 +25370,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -19091,1912 +25492,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -21179,7 +28521,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -21793,42 +29134,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21852,78 +29193,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -28906,7 +36290,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -28952,10 +36336,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -29004,7 +36388,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h index bda89a8d73..33b5008bb0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; @@ -396,6 +395,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -986,18 +1203,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1159,110 +1376,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1341,10 +1454,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1674,7 +1811,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1736,36 +1873,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1831,7 +1968,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -1931,7 +2067,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2522,20 +2658,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2544,69 +2680,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2622,42 +2772,42 @@ typedef struct #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2666,71 +2816,72 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2768,6 +2919,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2794,7 +2946,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -2974,6 +3125,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -2994,7 +3146,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3043,7 +3194,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3052,7 +3204,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3420,7 +3572,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3648,6 +3799,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -3921,7 +4073,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4192,7 +4344,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4229,7 +4381,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4266,7 +4418,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4303,7 +4455,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4678,6 +4830,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -5564,6 +5807,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -16622,6 +21430,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -17303,7 +22112,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -18184,766 +22993,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -18960,85 +25336,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -19057,1912 +25458,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -21145,7 +28487,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -21759,42 +29100,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -21818,78 +29159,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -28872,7 +36256,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -28918,10 +36302,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -28970,7 +36354,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h index bbfc353569..1b914cfc74 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; @@ -430,6 +429,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1020,18 +1237,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1193,110 +1410,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1375,10 +1488,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1708,7 +1845,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1770,36 +1907,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1865,7 +2002,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -1965,7 +2101,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2604,20 +2740,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2626,69 +2762,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2704,43 +2854,43 @@ typedef struct #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2749,72 +2899,73 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2852,6 +3003,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2878,7 +3030,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3060,6 +3211,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3080,7 +3232,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3129,7 +3280,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3138,7 +3290,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3506,7 +3658,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3734,6 +3885,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4007,7 +4159,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4278,7 +4430,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4315,7 +4467,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4352,7 +4504,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4389,7 +4541,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4764,6 +4916,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -5795,6 +6038,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -16853,6 +21661,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -17534,7 +22343,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -18415,766 +23224,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -19191,85 +25567,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -19288,1924 +25689,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -21388,7 +28718,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -22002,42 +29331,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -22061,78 +29390,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -29115,7 +36487,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -29161,13 +36533,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -29215,7 +36587,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h index ff110729cb..3386f431c6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; @@ -396,6 +395,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -986,18 +1203,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1159,110 +1376,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1341,10 +1454,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1674,7 +1811,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1736,36 +1873,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1831,7 +1968,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -1931,7 +2067,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2570,20 +2706,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2592,69 +2728,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2670,43 +2820,43 @@ typedef struct #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2715,72 +2865,73 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2818,6 +2969,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2844,7 +2996,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3026,6 +3177,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3046,7 +3198,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3095,7 +3246,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3104,7 +3256,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3472,7 +3624,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3700,6 +3851,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -3973,7 +4125,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4244,7 +4396,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4281,7 +4433,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4318,7 +4470,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4355,7 +4507,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4730,6 +4882,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -5761,6 +6004,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -16819,6 +21627,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -17500,7 +22309,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -18381,766 +23190,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -19157,85 +25533,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -19254,1924 +25655,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -21354,7 +28684,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -21968,42 +29297,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -22027,78 +29356,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -29081,7 +36453,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -29127,13 +36499,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -29181,7 +36553,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h index 96c40248d2..d075c6843c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -531,6 +530,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1121,18 +1338,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1294,110 +1511,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1476,10 +1589,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1809,7 +1946,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1871,36 +2008,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1966,7 +2103,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2066,7 +2202,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2657,20 +2793,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2679,69 +2815,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2756,48 +2906,48 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2806,71 +2956,72 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2908,6 +3059,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2934,7 +3086,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3118,6 +3269,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3138,7 +3290,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3187,7 +3338,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3196,7 +3348,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3564,7 +3716,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3792,6 +3943,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4065,7 +4217,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4336,7 +4488,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4373,7 +4525,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4410,7 +4562,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4447,7 +4599,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4822,6 +4974,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7149,6 +7392,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -18220,6 +23028,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -18901,7 +23710,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -19782,766 +24591,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -20558,85 +26934,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -20655,1926 +27056,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -22757,7 +30085,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -23371,42 +30698,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23430,78 +30757,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -30489,7 +37859,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -30535,10 +37905,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -30587,7 +37957,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h index 5ffaded66a..19207bc94c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -497,6 +496,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1087,18 +1304,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1260,110 +1477,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1442,10 +1555,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1775,7 +1912,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1837,36 +1974,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1932,7 +2069,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2032,7 +2168,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2623,20 +2759,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2645,69 +2781,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2722,48 +2872,48 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2772,71 +2922,72 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2874,6 +3025,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2900,7 +3052,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3084,6 +3235,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3104,7 +3256,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3153,7 +3304,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3162,7 +3314,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3530,7 +3682,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3758,6 +3909,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4031,7 +4183,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4302,7 +4454,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4339,7 +4491,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4376,7 +4528,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4413,7 +4565,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4788,6 +4940,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7115,6 +7358,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -18186,6 +22994,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -18867,7 +23676,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -19748,766 +24557,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -20524,85 +26900,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -20621,1926 +27022,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -22723,7 +30051,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -23337,42 +30664,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23396,78 +30723,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -30455,7 +37825,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -30501,10 +37871,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -30553,7 +37923,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h index 1538aa9490..6450ca755a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -531,6 +530,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1121,18 +1338,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1294,110 +1511,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1476,10 +1589,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1809,7 +1946,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1871,36 +2008,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1966,7 +2103,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2066,7 +2202,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2705,20 +2841,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2727,69 +2863,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2804,49 +2954,49 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2855,72 +3005,73 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2958,6 +3109,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2984,7 +3136,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3170,6 +3321,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3190,7 +3342,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3239,7 +3390,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3248,7 +3400,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3616,7 +3768,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3844,6 +3995,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4117,7 +4269,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4388,7 +4540,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4425,7 +4577,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4462,7 +4614,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4499,7 +4651,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4874,6 +5026,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7346,6 +7589,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -18417,6 +23225,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -19098,7 +23907,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -19979,766 +24788,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -20755,85 +27131,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -20852,1938 +27253,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -22966,7 +30282,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -23580,42 +30895,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23639,78 +30954,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -30698,7 +38056,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -30744,13 +38102,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -30798,7 +38156,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h index b72594d67e..dd60e2bf63 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -497,6 +496,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1087,18 +1304,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1260,110 +1477,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1442,10 +1555,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1775,7 +1912,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1837,36 +1974,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1932,7 +2069,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2032,7 +2168,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2671,20 +2807,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2693,69 +2829,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2770,49 +2920,49 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2821,72 +2971,73 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2924,6 +3075,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2950,7 +3102,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3136,6 +3287,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3156,7 +3308,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3205,7 +3356,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3214,7 +3366,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3582,7 +3734,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3810,6 +3961,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4083,7 +4235,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4354,7 +4506,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4391,7 +4543,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4428,7 +4580,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4465,7 +4617,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4840,6 +4992,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7312,6 +7555,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -18383,6 +23191,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -19064,7 +23873,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -19945,766 +24754,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -20721,85 +27097,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -20818,1938 +27219,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -22932,7 +30248,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -23546,42 +30861,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23605,78 +30920,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -30664,7 +38022,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -30710,13 +38068,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -30764,7 +38122,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h index 384f6073d3..56b82fde2a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -531,6 +530,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1121,18 +1338,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1294,110 +1511,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1476,10 +1589,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1809,7 +1946,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1871,36 +2008,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1966,7 +2103,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2066,7 +2202,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2657,20 +2793,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2679,69 +2815,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2756,48 +2906,48 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2806,71 +2956,72 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2908,6 +3059,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2934,7 +3086,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3118,6 +3269,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3138,7 +3290,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3187,7 +3338,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3196,7 +3348,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3564,7 +3716,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3792,6 +3943,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4065,7 +4217,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4336,7 +4488,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4373,7 +4525,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4410,7 +4562,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4447,7 +4599,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4822,6 +4974,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7149,6 +7392,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -18220,6 +23028,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -18901,7 +23710,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -19782,766 +24591,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -20558,85 +26934,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -20655,1926 +27056,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -22757,7 +30085,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -23371,42 +30698,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23430,78 +30757,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -30489,7 +37859,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -30535,10 +37905,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -30587,7 +37957,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h index a86122ac4f..a22cc371ff 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -497,6 +496,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1087,18 +1304,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1260,110 +1477,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1442,10 +1555,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1775,7 +1912,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1837,36 +1974,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1932,7 +2069,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2032,7 +2168,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2623,20 +2759,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2645,69 +2781,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2722,48 +2872,48 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2772,71 +2922,72 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2874,6 +3025,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2900,7 +3052,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3084,6 +3235,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3104,7 +3256,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3153,7 +3304,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3162,7 +3314,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3530,7 +3682,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3758,6 +3909,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4031,7 +4183,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4302,7 +4454,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4339,7 +4491,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4376,7 +4528,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4413,7 +4565,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4788,6 +4940,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7115,6 +7358,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -18186,6 +22994,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -18867,7 +23676,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -19748,766 +24557,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -20524,85 +26900,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -20621,1926 +27022,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -22723,7 +30051,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -23337,42 +30664,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23396,78 +30723,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -30455,7 +37825,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -30501,10 +37871,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -30553,7 +37923,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h index 8a21736f8a..32d003d9cf 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -531,6 +530,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1121,18 +1338,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1294,110 +1511,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1476,10 +1589,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1809,7 +1946,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1871,36 +2008,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1966,7 +2103,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2066,7 +2202,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2705,20 +2841,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2727,69 +2863,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2804,49 +2954,49 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2855,72 +3005,73 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2958,6 +3109,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2984,7 +3136,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3170,6 +3321,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3190,7 +3342,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3239,7 +3390,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3248,7 +3400,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3616,7 +3768,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3844,6 +3995,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4117,7 +4269,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4388,7 +4540,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4425,7 +4577,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4462,7 +4614,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4499,7 +4651,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4874,6 +5026,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7346,6 +7589,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -18417,6 +23225,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -19098,7 +23907,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -19979,766 +24788,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -20755,85 +27131,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -20852,1938 +27253,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -22966,7 +30282,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -23580,42 +30895,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23639,78 +30954,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -30698,7 +38056,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -30744,13 +38102,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -30798,7 +38156,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h index 38af1becd2..aa4aa280b4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -497,6 +496,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1087,18 +1304,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1260,110 +1477,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1442,10 +1555,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1775,7 +1912,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1837,36 +1974,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -1932,7 +2069,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2032,7 +2168,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2671,20 +2807,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2693,69 +2829,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2770,49 +2920,49 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2821,72 +2971,73 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) /*!< MPU_APB4 */ -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2924,6 +3075,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -2950,7 +3102,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3136,6 +3287,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3156,7 +3308,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3205,7 +3356,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3214,7 +3366,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3582,7 +3734,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3810,6 +3961,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4083,7 +4235,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4354,7 +4506,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4391,7 +4543,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4428,7 +4580,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4465,7 +4617,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4840,6 +4992,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7312,6 +7555,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -18383,6 +23191,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -19064,7 +23873,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -19945,766 +24754,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -20721,85 +27097,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -20818,1938 +27219,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -22932,7 +30248,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -23546,42 +30861,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -23605,78 +30920,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -30664,7 +38022,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -30710,13 +38068,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -30764,7 +38122,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* USBPHYC VERSION ********************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h index 45f2fc4739..565822a3bd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -531,6 +530,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1208,18 +1425,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1381,110 +1598,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1563,10 +1676,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1896,7 +2033,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1958,36 +2095,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -2053,7 +2190,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2153,7 +2289,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2770,20 +2906,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2792,69 +2928,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2869,48 +3019,48 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2919,73 +3069,74 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) -#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) +#define GPU_BASE (AHB6_PERIPH_BASE + 0x1000000) /*!< MPU_APB4 */ -#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000) -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define DSI_BASE (APB4_PERIPH_BASE + 0x0000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -3023,6 +3174,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -3049,7 +3201,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3233,6 +3384,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3253,7 +3405,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3302,7 +3453,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3312,7 +3464,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3681,7 +3833,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3909,6 +4060,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4182,7 +4334,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4453,7 +4605,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4490,7 +4642,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4527,7 +4679,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4564,7 +4716,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4939,6 +5091,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7266,6 +7509,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -19445,6 +24253,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -20126,7 +24935,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -21007,766 +25816,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -21783,85 +28159,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -21880,1947 +28281,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - -/******************** Bit definition for RCC_DSICKSELR register********************/ -#define RCC_DSICKSELR_DSISRC_Pos (0U) -#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ -#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/ -#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */ -#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DSIRST B(4) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DSIRST B(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_GPURST B(5) -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DSIEN B(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_DSIEN B(4) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_DSIEN B(4) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_DSIEN B(4) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_GPUEN B(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_GPUEN B(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_DSILPEN B(4) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_DSILPEN B(4) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN B(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -24003,7 +31310,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -24617,42 +31923,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24676,78 +31982,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -31735,7 +39084,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -31781,10 +39130,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -31833,7 +39182,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DSI VERSION ********************************/ #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h index 014af6090e..5cde4836d6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -497,6 +496,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1174,18 +1391,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1347,110 +1564,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1529,10 +1642,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1862,7 +1999,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1924,36 +2061,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -2019,7 +2156,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2119,7 +2255,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2736,20 +2872,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2758,69 +2894,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2835,48 +2985,48 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2885,73 +3035,74 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) -#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) +#define GPU_BASE (AHB6_PERIPH_BASE + 0x1000000) /*!< MPU_APB4 */ -#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000) -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define DSI_BASE (APB4_PERIPH_BASE + 0x0000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2989,6 +3140,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -3015,7 +3167,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3199,6 +3350,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3219,7 +3371,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3268,7 +3419,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3278,7 +3430,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3647,7 +3799,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3875,6 +4026,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4148,7 +4300,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4419,7 +4571,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4456,7 +4608,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4493,7 +4645,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4530,7 +4682,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4905,6 +5057,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7232,6 +7475,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -19411,6 +24219,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -20092,7 +24901,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -20973,766 +25782,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -21749,85 +28125,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -21846,1947 +28247,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - -/******************** Bit definition for RCC_DSICKSELR register********************/ -#define RCC_DSICKSELR_DSISRC_Pos (0U) -#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ -#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/ -#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */ -#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DSIRST B(4) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DSIRST B(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_GPURST B(5) -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DSIEN B(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_DSIEN B(4) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_DSIEN B(4) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_DSIEN B(4) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_GPUEN B(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_GPUEN B(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_DSILPEN B(4) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_DSILPEN B(4) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN B(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -23969,7 +31276,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -24583,42 +31889,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24642,78 +31948,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -31701,7 +39050,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -31747,10 +39096,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -31799,7 +39148,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DSI VERSION ********************************/ #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h index 169f07998a..131b2f7533 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -531,6 +530,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1208,18 +1425,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1381,110 +1598,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1563,10 +1676,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1896,7 +2033,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1958,36 +2095,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -2053,7 +2190,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2153,7 +2289,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2818,20 +2954,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2840,69 +2976,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2917,49 +3067,49 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2968,74 +3118,75 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) -#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) +#define GPU_BASE (AHB6_PERIPH_BASE + 0x1000000) /*!< MPU_APB4 */ -#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000) -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define DSI_BASE (APB4_PERIPH_BASE + 0x0000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -3073,6 +3224,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -3099,7 +3251,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3285,6 +3436,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3305,7 +3457,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3354,7 +3505,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3364,7 +3516,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3733,7 +3885,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3961,6 +4112,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4234,7 +4386,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4505,7 +4657,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4542,7 +4694,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4579,7 +4731,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4616,7 +4768,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4991,6 +5143,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7463,6 +7706,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -19642,6 +24450,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -20323,7 +25132,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -21204,766 +26013,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -21980,85 +28356,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -22077,1959 +28478,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - -/******************** Bit definition for RCC_DSICKSELR register********************/ -#define RCC_DSICKSELR_DSISRC_Pos (0U) -#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ -#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/ -#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */ -#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DSIRST B(4) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DSIRST B(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_GPURST B(5) -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DSIEN B(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_DSIEN B(4) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_DSIEN B(4) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_DSIEN B(4) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_GPUEN B(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_GPUEN B(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_DSILPEN B(4) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_DSILPEN B(4) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN B(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -24212,7 +31507,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -24826,42 +32120,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24885,78 +32179,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -31944,7 +39281,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -31990,13 +39327,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -32044,7 +39381,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DSI VERSION ********************************/ #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h index dc809520c5..550ad156c5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -497,6 +496,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1174,18 +1391,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1347,110 +1564,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1529,10 +1642,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1862,7 +1999,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1924,36 +2061,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -2019,7 +2156,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2119,7 +2255,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2784,20 +2920,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2806,69 +2942,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2883,49 +3033,49 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2934,74 +3084,75 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) -#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) +#define GPU_BASE (AHB6_PERIPH_BASE + 0x1000000) /*!< MPU_APB4 */ -#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000) -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define DSI_BASE (APB4_PERIPH_BASE + 0x0000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -3039,6 +3190,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -3065,7 +3217,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3251,6 +3402,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3271,7 +3423,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3320,7 +3471,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3330,7 +3482,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3699,7 +3851,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3927,6 +4078,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4200,7 +4352,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4471,7 +4623,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4508,7 +4660,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4545,7 +4697,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4582,7 +4734,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4957,6 +5109,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7429,6 +7672,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -19608,6 +24416,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -20289,7 +25098,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -21170,766 +25979,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -21946,85 +28322,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -22043,1959 +28444,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - -/******************** Bit definition for RCC_DSICKSELR register********************/ -#define RCC_DSICKSELR_DSISRC_Pos (0U) -#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ -#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/ -#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */ -#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DSIRST B(4) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DSIRST B(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_GPURST B(5) -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DSIEN B(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_DSIEN B(4) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_DSIEN B(4) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_DSIEN B(4) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_GPUEN B(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_GPUEN B(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_DSILPEN B(4) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_DSILPEN B(4) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN B(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -24178,7 +31473,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -24792,42 +32086,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24851,78 +32145,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -31910,7 +39247,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -31956,13 +39293,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -32010,7 +39347,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DSI VERSION ********************************/ #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h index 65b355c1cb..61dc5a88c0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -531,6 +530,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1208,18 +1425,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1381,110 +1598,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1563,10 +1676,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1896,7 +2033,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1958,36 +2095,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -2053,7 +2190,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2153,7 +2289,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2770,20 +2906,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2792,69 +2928,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2869,48 +3019,48 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2919,73 +3069,74 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) -#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) +#define GPU_BASE (AHB6_PERIPH_BASE + 0x1000000) /*!< MPU_APB4 */ -#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000) -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define DSI_BASE (APB4_PERIPH_BASE + 0x0000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -3023,6 +3174,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -3049,7 +3201,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3233,6 +3384,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3253,7 +3405,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3302,7 +3453,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3312,7 +3464,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3681,7 +3833,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3909,6 +4060,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4182,7 +4334,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4453,7 +4605,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4490,7 +4642,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4527,7 +4679,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4564,7 +4716,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4939,6 +5091,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7266,6 +7509,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -19445,6 +24253,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -20126,7 +24935,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -21007,766 +25816,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -21783,85 +28159,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -21880,1947 +28281,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - -/******************** Bit definition for RCC_DSICKSELR register********************/ -#define RCC_DSICKSELR_DSISRC_Pos (0U) -#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ -#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/ -#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */ -#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DSIRST B(4) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DSIRST B(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_GPURST B(5) -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DSIEN B(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_DSIEN B(4) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_DSIEN B(4) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_DSIEN B(4) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_GPUEN B(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_GPUEN B(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_DSILPEN B(4) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_DSILPEN B(4) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN B(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -24003,7 +31310,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -24617,42 +31923,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24676,78 +31982,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -31735,7 +39084,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -31781,10 +39130,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -31833,7 +39182,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DSI VERSION ********************************/ #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h index 738f3c8712..031c3c7cd7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -497,6 +496,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1174,18 +1391,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1347,110 +1564,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1529,10 +1642,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1862,7 +1999,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1924,36 +2061,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -2019,7 +2156,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2119,7 +2255,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2736,20 +2872,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2758,69 +2894,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2835,48 +2985,48 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2885,73 +3035,74 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) -#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) +#define GPU_BASE (AHB6_PERIPH_BASE + 0x1000000) /*!< MPU_APB4 */ -#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000) -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define DSI_BASE (APB4_PERIPH_BASE + 0x0000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -2989,6 +3140,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -3015,7 +3167,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3199,6 +3350,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3219,7 +3371,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3268,7 +3419,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3278,7 +3430,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3647,7 +3799,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3875,6 +4026,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4148,7 +4300,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4419,7 +4571,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4456,7 +4608,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4493,7 +4645,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4530,7 +4682,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4905,6 +5057,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7232,6 +7475,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -19411,6 +24219,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -20092,7 +24901,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -20973,766 +25782,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -21749,85 +28125,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -21846,1947 +28247,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - -/******************** Bit definition for RCC_DSICKSELR register********************/ -#define RCC_DSICKSELR_DSISRC_Pos (0U) -#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ -#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/ -#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */ -#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DSIRST B(4) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DSIRST B(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_GPURST B(5) -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DSIEN B(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_DSIEN B(4) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_DSIEN B(4) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_DSIEN B(4) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_GPUEN B(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_GPUEN B(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_DSILPEN B(4) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_DSILPEN B(4) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN B(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -23969,7 +31276,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -24583,42 +31889,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24642,78 +31948,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -31701,7 +39050,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -31747,10 +39096,10 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ @@ -31799,7 +39148,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DSI VERSION ********************************/ #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h index 60ae69a3f1..a998be701d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h @@ -83,12 +83,12 @@ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ - /****** STM32 specific Interrupt Numbers ****************************************************************************/ + /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ - RESERVED_36 = 36, /*!< RESERVED interrupt */ + TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ @@ -329,8 +329,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -344,7 +344,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -531,6 +530,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1208,18 +1425,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1381,110 +1598,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1563,10 +1676,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1896,7 +2033,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1958,36 +2095,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -2053,7 +2190,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2153,7 +2289,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2818,20 +2954,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x30000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x38000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2840,69 +2976,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2917,49 +3067,49 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2968,74 +3118,75 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) -#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) +#define GPU_BASE (AHB6_PERIPH_BASE + 0x1000000) /*!< MPU_APB4 */ -#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000) -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define DSI_BASE (APB4_PERIPH_BASE + 0x0000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -3073,6 +3224,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -3099,7 +3251,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3285,6 +3436,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3305,7 +3457,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3354,7 +3505,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3364,7 +3516,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3733,7 +3885,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3961,6 +4112,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4234,7 +4386,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4505,7 +4657,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4542,7 +4694,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4579,7 +4731,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4616,7 +4768,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4991,6 +5143,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7463,6 +7706,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -19642,6 +24450,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -20323,7 +25132,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -21204,766 +26013,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -21980,85 +28356,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -22077,1959 +28478,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - -/******************** Bit definition for RCC_DSICKSELR register********************/ -#define RCC_DSICKSELR_DSISRC_Pos (0U) -#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ -#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/ -#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */ -#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DSIRST B(4) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DSIRST B(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_GPURST B(5) -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DSIEN B(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_DSIEN B(4) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_DSIEN B(4) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_DSIEN B(4) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_GPUEN B(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_GPUEN B(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_DSILPEN B(4) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_DSILPEN B(4) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN B(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -24212,7 +31507,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -24826,42 +32120,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24885,78 +32179,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -31944,7 +39281,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -31990,13 +39327,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -32044,7 +39381,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DSI VERSION ********************************/ #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h index 7e58d59ec3..f63193b89a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h @@ -295,8 +295,8 @@ typedef struct __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ uint32_t RESERVED10; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */ - uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0x0D0 */ + uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */ @@ -310,7 +310,6 @@ typedef struct __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ - } ADC_Common_TypeDef; /** @@ -497,6 +496,224 @@ typedef struct __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */ } DAC_TypeDef; +/* + * @brief DDRCTRL block description (DDRCTRL) + */ +typedef struct +{ + __IO uint32_t MSTR; /*!< DDRCTRL master register 0 Address offset: 0x000 */ + __IO uint32_t STAT; /*!< DDRCTRL operating mode status register Address offset: 0x004 */ + uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x008-0x00C */ + __IO uint32_t MRCTRL0; /*!< DDRCTRL mode register read/write control register 0 Address offset: 0x010 */ + __IO uint32_t MRCTRL1; /*!< DDRCTRL mode register read/write control register 1 Address offset: 0x014 */ + __IO uint32_t MRSTAT; /*!< DDRCTRL mode register read/write status register Address offset: 0x018 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t DERATEEN; /*!< DDRCTRL temperature derate enable register Address offset: 0x020 */ + __IO uint32_t DERATEINT; /*!< DDRCTRL temperature derate interval register Address offset: 0x024 */ + uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x028-0x02C */ + __IO uint32_t PWRCTL; /*!< DDRCTRL low power control register Address offset: 0x030 */ + __IO uint32_t PWRTMG; /*!< DDRCTRL low power timing register Address offset: 0x034 */ + __IO uint32_t HWLPCTL; /*!< DDRCTRL hardware low power control register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */ + __IO uint32_t RFSHCTL0; /*!< DDRCTRL refresh control register 0 Address offset: 0x050 */ + uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0x054-0x05C */ + __IO uint32_t RFSHCTL3; /*!< DDRCTRL refresh control register 3 Address offset: 0x060 */ + __IO uint32_t RFSHTMG; /*!< DDRCTRL refresh timing register Address offset: 0x064 */ + uint32_t RESERVED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */ + __IO uint32_t CRCPARCTL0; /*!< DDRCTRL CRC parity control register 0 Address offset: 0x0C0 */ + uint32_t RESERVED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */ + __IO uint32_t CRCPARSTAT; /*!< DDRCTRL CRC parity status register Address offset: 0x0CC */ + __IO uint32_t INIT0; /*!< DDRCTRL SDRAM initialization register 0 Address offset: 0x0D0 */ + __IO uint32_t INIT1; /*!< DDRCTRL SDRAM initialization register 1 Address offset: 0x0D4 */ + __IO uint32_t INIT2; /*!< DDRCTRL SDRAM initialization register 2 Address offset: 0x0D8 */ + __IO uint32_t INIT3; /*!< DDRCTRL SDRAM initialization register 3 Address offset: 0x0DC */ + __IO uint32_t INIT4; /*!< DDRCTRL SDRAM initialization register 4 Address offset: 0x0E0 */ + __IO uint32_t INIT5; /*!< DDRCTRL SDRAM initialization register 5 Address offset: 0x0E4 */ + uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */ + __IO uint32_t DIMMCTL; /*!< DDRCTRL DIMM control register Address offset: 0x0F0 */ + uint32_t RESERVED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */ + __IO uint32_t DRAMTMG0; /*!< DDRCTRL SDRAM timing register 0 Address offset: 0x100 */ + __IO uint32_t DRAMTMG1; /*!< DDRCTRL SDRAM timing register 1 Address offset: 0x104 */ + __IO uint32_t DRAMTMG2; /*!< DDRCTRL SDRAM timing register 2 Address offset: 0x108 */ + __IO uint32_t DRAMTMG3; /*!< DDRCTRL SDRAM timing register 3 Address offset: 0x10C */ + __IO uint32_t DRAMTMG4; /*!< DDRCTRL SDRAM timing register 4 Address offset: 0x110 */ + __IO uint32_t DRAMTMG5; /*!< DDRCTRL SDRAM timing register 5 Address offset: 0x114 */ + __IO uint32_t DRAMTMG6; /*!< DDRCTRL SDRAM timing register 6 Address offset: 0x118 */ + __IO uint32_t DRAMTMG7; /*!< DDRCTRL SDRAM timing register 7 Address offset: 0x11C */ + __IO uint32_t DRAMTMG8; /*!< DDRCTRL SDRAM timing register 8 Address offset: 0x120 */ + uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x124-0x134 */ + __IO uint32_t DRAMTMG14; /*!< DDRCTRL SDRAM timing register 14 Address offset: 0x138 */ + __IO uint32_t DRAMTMG15; /*!< DDRCTRL SDRAM timing register 15 Address offset: 0x13C */ + uint32_t RESERVED10[16]; /*!< Reserved Address offset: 0x140-0x17C */ + __IO uint32_t ZQCTL0; /*!< DDRCTRL ZQ control register 0 Address offset: 0x180 */ + __IO uint32_t ZQCTL1; /*!< DDRCTRL ZQ control register 1 Address offset: 0x184 */ + __IO uint32_t ZQCTL2; /*!< DDRCTRL ZQ control register 2 Address offset: 0x188 */ + __IO uint32_t ZQSTAT; /*!< DDRCTRL ZQ status register Address offset: 0x18C */ + __IO uint32_t DFITMG0; /*!< DDRCTRL DFI timing register 0 Address offset: 0x190 */ + __IO uint32_t DFITMG1; /*!< DDRCTRL DFI timing register 1 Address offset: 0x194 */ + __IO uint32_t DFILPCFG0; /*!< DDRCTRL low power configuration register 0 Address offset: 0x198 */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x19C */ + __IO uint32_t DFIUPD0; /*!< DDRCTRL DFI update register 0 Address offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /*!< DDRCTRL DFI update register 1 Address offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /*!< DDRCTRL DFI update register 2 Address offset: 0x1A8 */ + uint32_t RESERVED12; /*!< Reserved Address offset: 0x1AC */ + __IO uint32_t DFIMISC; /*!< DDRCTRL DFI miscellaneous control register Address offset: 0x1B0 */ + uint32_t RESERVED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */ + __IO uint32_t DFISTAT; /*!< DDRCTRL DFI status register Address offset: 0x1BC */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0x1C0 */ + __IO uint32_t DFIPHYMSTR; /*!< DDRCTRL DFI PHY master register Address offset: 0x1C4 */ + uint32_t RESERVED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */ + __IO uint32_t ADDRMAP1; /*!< DDRCTRL address map register 1 Address offset: 0x204 */ + __IO uint32_t ADDRMAP2; /*!< DDRCTRL address map register 2 Address offset: 0x208 */ + __IO uint32_t ADDRMAP3; /*!< DDRCTRL address map register 3 Address offset: 0x20C */ + __IO uint32_t ADDRMAP4; /*!< DDRCTRL address map register 4 Address offset: 0x210 */ + __IO uint32_t ADDRMAP5; /*!< DDRCTRL address map register 5 Address offset: 0x214 */ + __IO uint32_t ADDRMAP6; /*!< DDRCTRL address register 6 Address offset: 0x218 */ + uint32_t RESERVED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */ + __IO uint32_t ADDRMAP9; /*!< DDRCTRL address map register 9 Address offset: 0x224 */ + __IO uint32_t ADDRMAP10; /*!< DDRCTRL address map register 10 Address offset: 0x228 */ + __IO uint32_t ADDRMAP11; /*!< DDRCTRL address map register 11 Address offset: 0x22C */ + uint32_t RESERVED17[4]; /*!< Reserved Address offset: 0x230-0x23C */ + __IO uint32_t ODTCFG; /*!< DDRCTRL ODT configuration register Address offset: 0x240 */ + __IO uint32_t ODTMAP; /*!< DDRCTRL ODT/Rank map register Address offset: 0x244 */ + uint32_t RESERVED18[2]; /*!< Reserved Address offset: 0x248-0x24C */ + __IO uint32_t SCHED; /*!< DDRCTRL scheduler control register Address offset: 0x250 */ + __IO uint32_t SCHED1; /*!< DDRCTRL scheduler control register 1 Address offset: 0x254 */ + uint32_t RESERVED19; /*!< Reserved Address offset: 0x258 */ + __IO uint32_t PERFHPR1; /*!< DDRCTRL high priority read CAM register 1 Address offset: 0x25C */ + uint32_t RESERVED20; /*!< Reserved Address offset: 0x260 */ + __IO uint32_t PERFLPR1; /*!< DDRCTRL low priority read CAM register 1 Address offset: 0x264 */ + uint32_t RESERVED21; /*!< Reserved Address offset: 0x268 */ + __IO uint32_t PERFWR1; /*!< DDRCTRL write CAM register 1 Address offset: 0x26C */ + uint32_t RESERVED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */ + __IO uint32_t DBG0; /*!< DDRCTRL debug register 0 Address offset: 0x300 */ + __IO uint32_t DBG1; /*!< DDRCTRL debug register 1 Address offset: 0x304 */ + __IO uint32_t DBGCAM; /*!< DDRCTRL CAM debug register Address offset: 0x308 */ + __IO uint32_t DBGCMD; /*!< DDRCTRL command debug register Address offset: 0x30C */ + __IO uint32_t DBGSTAT; /*!< DDRCTRL status debug register Address offset: 0x310 */ + uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x314-0x31C */ + __IO uint32_t SWCTL; /*!< DDRCTRL software register programming control enable Address offset: 0x320 */ + __IO uint32_t SWSTAT; /*!< DDRCTRL software register programming control status Address offset: 0x324 */ + uint32_t RESERVED24[17]; /*!< Reserved Address offset: 0x328-0x368 */ + __IO uint32_t POISONCFG; /*!< DDRCTRL AXI Poison configuration register Address offset: 0x36C */ + __IO uint32_t POISONSTAT; /*!< DDRCTRL AXI Poison status register Address offset: 0x370 */ + uint32_t RESERVED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */ + __IO uint32_t PSTAT; /*!< DDRCTRL port status register Address offset: 0x3FC */ + __IO uint32_t PCCFG; /*!< DDRCTRL port common configuration register Address offset: 0x400 */ + __IO uint32_t PCFGR_0; /*!< DDRCTRL port 0 configuration read register Address offset: 0x404 */ + __IO uint32_t PCFGW_0; /*!< DDRCTRL port 0 configuration write register Address offset: 0x408 */ + uint32_t RESERVED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */ + __IO uint32_t PCTRL_0; /*!< DDRCTRL port 0 control register Address offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /*!< DDRCTRL port 0 read Q0S configuration register 0 Address offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /*!< DDRCTRL port 0 read Q0S configuration register 1 Address offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /*!< DDRCTRL port 0 write Q0S configuration register 0 Address offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /*!< DDRCTRL port 0 write Q0S configuration register 1 Address offset: 0x4A0 */ + uint32_t RESERVED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */ + __IO uint32_t PCFGR_1; /*!< DDRCTRL port 1 configuration read register Address offset: 0x4B4 */ + __IO uint32_t PCFGW_1; /*!< DDRCTRL port 1 configuration write register Address offset: 0x4B8 */ + uint32_t RESERVED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */ + __IO uint32_t PCTRL_1; /*!< DDRCTRL port 1 control register Address offset: 0x540 */ + __IO uint32_t PCFGQOS0_1; /*!< DDRCTRL port 1 read Q0S configuration register 0 Address offset: 0x544 */ + __IO uint32_t PCFGQOS1_1; /*!< DDRCTRL port 1 read Q0S configuration register 1 Address offset: 0x548 */ + __IO uint32_t PCFGWQOS0_1; /*!< DDRCTRL port 1 write Q0S configuration register 0 Address offset: 0x54C */ + __IO uint32_t PCFGWQOS1_1; /*!< DDRCTRL port 1 write Q0S configuration register 1 Address offset: 0x550 */ +} DDRCTRL_TypeDef; + +/* + * @brief DDRPERFM block description (DDRPERFM) + */ +typedef struct +{ + __IO uint32_t CTL; /*!< DDRPERFM control register Address offset: 0x000 */ + __IO uint32_t CFG; /*!< DDRPERFM configurationl register Address offset: 0x004 */ + __IO uint32_t STATUS; /*!< DDRPERFM status register Address offset: 0x008 */ + __IO uint32_t CCR; /*!< DDRPERFM counter clear register Address offset: 0x00C */ + __IO uint32_t IER; /*!< DDRPERFM interrupt enable register Address offset: 0x010 */ + __IO uint32_t ISR; /*!< DDRPERFM interrupt status register Address offset: 0x014 */ + __IO uint32_t ICR; /*!< DDRPERFM interrupt clear register Address offset: 0x018 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x01C */ + __IO uint32_t TCNT; /*!< DDRPERFM time counter register Address offset: 0x020 */ + uint32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */ + __IO uint32_t CNT0; /*!< DDRPERFM event counter 0 register Address offset: 0x030 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x034 */ + __IO uint32_t CNT1; /*!< DDRPERFM event counter 1 register Address offset: 0x038 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x03C */ + __IO uint32_t CNT2; /*!< DDRPERFM event counter 2 register Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x044 */ + __IO uint32_t CNT3; /*!< DDRPERFM event counter 3 register Address offset: 0x048 */ + uint32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */ + __IO uint32_t HWCFG; /*!< DDRPERFM hardware configuration register Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< DDRPERFM version register Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< DDRPERFM ID register Address offset: 0x3F8 */ + __IO uint32_t SID; /*!< DDRPERFM magic ID register Address offset: 0x3FC */ +} DDRPERFM_TypeDef; + +/* + * @brief DDRPHYC block description (DDRPHYC) + */ +typedef struct +{ + __IO uint32_t RIDR; /*!< DDRPHYC revision ID register Address offset: 0x000 */ + __IO uint32_t PIR; /*!< DDRPHYC PHY initialization register Address offset: 0x004 */ + __IO uint32_t PGCR; /*!< DDRPHYC PHY global control register Address offset: 0x008 */ + __IO uint32_t PGSR; /*!< DDRPHYC PHY global status register Address offset: 0x00C */ + __IO uint32_t DLLGCR; /*!< DDRPHYC DDR global control register Address offset: 0x010 */ + __IO uint32_t ACDLLCR; /*!< DDRPHYC AC DLL control register Address offset: 0x014 */ + __IO uint32_t PTR0; /*!< DDRPHYC PT register 0 Address offset: 0x018 */ + __IO uint32_t PTR1; /*!< DDRPHYC PT register 1 Address offset: 0x01C */ + __IO uint32_t PTR2; /*!< DDRPHYC PT register 2 Address offset: 0x020 */ + __IO uint32_t ACIOCR; /*!< DDRPHYC ACIOC register Address offset: 0x024 */ + __IO uint32_t DXCCR; /*!< DDRPHYC DXCC register Address offset: 0x028 */ + __IO uint32_t DSGCR; /*!< DDRPHYC DSGC register Address offset: 0x02C */ + __IO uint32_t DCR; /*!< DDRPHYC DC register Address offset: 0x030 */ + __IO uint32_t DTPR0; /*!< DDRPHYC DTP register 0 Address offset: 0x034 */ + __IO uint32_t DTPR1; /*!< DDRPHYC DTP register 1 Address offset: 0x038 */ + __IO uint32_t DTPR2; /*!< DDRPHYC DTP register 2 Address offset: 0x03C */ + __IO uint32_t DDR3_MR0; /*!< DDRPHYC MR0 register for DDR3 Address offset: 0x040 */ + __IO uint32_t DDR3_MR1; /*!< DDRPHYC MR1 register for DDR3 Address offset: 0x044 */ + __IO uint32_t DDR3_MR2; /*!< DDRPHYC MR2 register for DDR3 Address offset: 0x048 */ + __IO uint32_t DDR3_MR3; /*!< DDRPHYC MR3 register for DDR3 Address offset: 0x04C */ + __IO uint32_t ODTCR; /*!< DDRPHYC ODTC register Address offset: 0x050 */ + __IO uint32_t DTAR; /*!< DDRPHYC DTA register Address offset: 0x054 */ + __IO uint32_t DTDR0; /*!< DDRPHYC DTD register 0 Address offset: 0x058 */ + __IO uint32_t DTDR1; /*!< DDRPHYC DTD register 1 Address offset: 0x05C */ + uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */ + __IO uint32_t GPR0; /*!< DDRPHYC general purpose register 0 Address offset: 0x178 */ + __IO uint32_t GPR1; /*!< DDRPHYC general purpose register 1 Address offset: 0x17C */ + __IO uint32_t ZQ0CR0; /*!< DDRPHYC ZQ0C register 0 Address offset: 0x180 */ + __IO uint32_t ZQ0CR1; /*!< DDRPHYC ZQ0CR1 register Address offset: 0x184 */ + __IO uint32_t ZQ0SR0; /*!< DDRPHYC ZQ0S register 0 Address offset: 0x188 */ + __IO uint32_t ZQ0SR1; /*!< DDRPHYC ZQ0S register 1 Address offset: 0x18C */ + uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */ + __IO uint32_t DX0GCR; /*!< DDRPHYC byte lane 0 GC register Address offset: 0x1C0 */ + __IO uint32_t DX0GSR0; /*!< DDRPHYC byte lane 0 GS register 0 Address offset: 0x1C4 */ + __IO uint32_t DX0GSR1; /*!< DDRPHYC byte lane 0 GS register 1 Address offset: 0x1C8 */ + __IO uint32_t DX0DLLCR; /*!< DDRPHYC byte lane 0 DLLC register Address offset: 0x1CC */ + __IO uint32_t DX0DQTR; /*!< DDRPHYC byte lane 0 DQT register Address offset: 0x1D0 */ + __IO uint32_t DX0DQSTR; /*!< DDRPHYC byte lane 0 DQST register Address offset: 0x1D4 */ + uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */ + __IO uint32_t DX1GCR; /*!< DDRPHYC byte lane 1 GC register Address offset: 0x200 */ + __IO uint32_t DX1GSR0; /*!< DDRPHYC byte lane 1 GS register 0 Address offset: 0x204 */ + __IO uint32_t DX1GSR1; /*!< DDRPHYC byte lane 1 GS register 1 Address offset: 0x208 */ + __IO uint32_t DX1DLLCR; /*!< DDRPHYC byte lane 1 DLLC register Address offset: 0x20C */ + __IO uint32_t DX1DQTR; /*!< DDRPHYC byte lane 1 DQT register Address offset: 0x210 */ + __IO uint32_t DX1DQSTR; /*!< DDRPHYC byte lane 1 DQST register Address offset: 0x214 */ + uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */ + __IO uint32_t DX2GCR; /*!< DDRPHYC byte lane 2 GC register Address offset: 0x240 */ + __IO uint32_t DX2GSR0; /*!< DDRPHYC byte lane 2 GS register 0 Address offset: 0x244 */ + __IO uint32_t DX2GSR1; /*!< DDRPHYC byte lane 2 GS register 1 Address offset: 0x248 */ + __IO uint32_t DX2DLLCR; /*!< DDRPHYC byte lane 2 DLLC register Address offset: 0x24C */ + __IO uint32_t DX2DQTR; /*!< DDRPHYC byte lane 2 DQT register Address offset: 0x250 */ + __IO uint32_t DX2DQSTR; /*!< DDRPHYC byte lane 2 DQST register Address offset: 0x254 */ + uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */ + __IO uint32_t DX3GCR; /*!< DDRPHYC byte lane 3 GC register Address offset: 0x280 */ + __IO uint32_t DX3GSR0; /*!< DDRPHYC byte lane 3 GS register 0 Address offset: 0x284 */ + __IO uint32_t DX3GSR1; /*!< DDRPHYC byte lane 3 GS register 1 Address offset: 0x288 */ + __IO uint32_t DX3DLLCR; /*!< DDRPHYC byte lane 3 DLLC register Address offset: 0x28C */ + __IO uint32_t DX3DQTR; /*!< DDRPHYC byte lane 3 DQT register Address offset: 0x290 */ + __IO uint32_t DX3DQSTR; /*!< DDRPHYC byte lane 3 DQST register Address offset: 0x294 */ +} DDRPHYC_TypeDef; + /** * @brief DFSDM module registers */ @@ -1174,18 +1391,18 @@ typedef struct { __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x14 */ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */ - __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */ - __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */ - uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */ + uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C-0x3F0 */ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */ @@ -1347,110 +1564,6 @@ typedef struct } LTDC_Layer_TypeDef; -/** - * @brief DDRPHYC DDR Physical Interface Control - */ -typedef struct -{ - __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */ - __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */ - __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */ - __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */ - __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */ - __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */ - __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */ - __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */ - __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */ - __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */ - __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */ - __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */ - __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */ - __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */ - __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */ - __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */ - __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */ - __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */ - __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */ - __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */ - __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */ - __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */ - __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */ - __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */ - uint32_t RESERVED0[24]; /*!< Reserved */ - __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */ - __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */ - __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */ - __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */ - __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */ - __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */ - __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */ - __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */ - uint32_t RESERVED1[8]; /*!< Reserved */ - __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */ - __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */ - __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */ - __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */ - __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */ - __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */ - __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */ - __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */ - __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */ - __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */ - __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */ - __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */ - __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */ - __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */ - __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */ - __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */ - __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */ - uint32_t RESERVED2[13]; /*!< Reserved */ - __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */ - __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */ - __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */ - __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */ - __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */ - __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */ - uint32_t RESERVED3[12]; /*!< Reserved */ - __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */ - __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */ - __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */ - __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */ - __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */ - __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */ - uint32_t RESERVED4[10]; /*!< Reserved */ - __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */ - __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */ - __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */ - __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */ - __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */ - __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */ - uint32_t RESERVED5[10]; /*!< Reserved */ - __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */ - __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */ - __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */ - __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */ - __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */ - __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */ - uint32_t RESERVED6[10]; /*!< Reserved */ - __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */ - __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */ - __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */ - __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */ - __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */ - __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */ -}DDRPHYC_TypeDef; - - -/** - * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL) - */ -typedef struct -{ - __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated */ -}DDRC_TypeDef; - - /** * @brief USBPHYC USB HS PHY Control */ @@ -1529,10 +1642,34 @@ typedef struct */ typedef struct { - __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */ - /* @TODO : TypeDef to be compleated if needed*/ + __IO uint32_t CNTCR; /*!< STGENC Counter Control Register, Address offset: 0x000 */ + uint32_t CNTSR; /*!< STGENC Counter Status Register, Address offset: 0x004 */ + __IO uint32_t CNTCVL; /*!< STGENC Current Counter Value Lower Register, Address offset: 0x008 */ + __IO uint32_t CNTCVU; /*!< STGENC Current Counter Value Upper Register, Address offset: 0x00C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */ + __IO uint32_t CNTFID0; /*!< STGENC Base Frequency ID Register, Address offset: 0x020 */ + uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENC Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0xFF0 */ }STGENC_TypeDef; +/** + * @brief STGENR System Timestamp Generator Read + */ +typedef struct +{ + __IO uint32_t CNTCVL; /*!< STGENR Current Counter Value Lower Register, Address offset: 0x000 */ + __IO uint32_t CNTCVU; /*!< STGENR Current Counter Value Upper Register, Address offset: 0x004 */ + uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */ + __IO uint32_t PIDR4; /*!< STGENR Peripheral ID4 Register, Address offset: 0xFD0 */ + __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */ + __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */ + __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */ +} STGENR_TypeDef; + + /** * @brief Firewall */ @@ -1862,7 +1999,7 @@ typedef struct __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */ - __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */ + __IO uint32_t RESERVED0x18; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */ @@ -1924,36 +2061,36 @@ typedef struct typedef struct { - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved */ - __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ - __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ - uint32_t RESERVED2[227]; /*!< Reserved */ - __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved */ + __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */ + __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */ + uint32_t RESERVED2[227]; /*!< Reserved */ + __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */ } RTC_TypeDef; @@ -2019,7 +2156,6 @@ typedef struct __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */ - } TAMP_TypeDef; @@ -2119,7 +2255,7 @@ typedef struct __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */ @@ -2784,20 +2920,20 @@ typedef struct /** @addtogroup Peripheral_memory_map * @{ */ -#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ -#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ +#define AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */ +#define AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */ #define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */ #define RETRAM_BASE MCU_AHB_RETRAM -#define SRAM_BASE MCU_AHB_SRAM +#define SRAM_BASE AHB_SRAM #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ +#define AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */ -#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ -#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ -#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ -#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ +#define FMC_NOR_MEM_BASE (AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */ +#define QSPI_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_NAND_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */ +#define STM_DATA_BASE (AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */ +#define DRAM_MEM_BASE (AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */ /*!< Device electronic signature memory map */ #define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */ @@ -2806,69 +2942,83 @@ typedef struct #define DV_BASE (0x50081000L) /*!< Device Version register base address */ /*!< Peripheral memory map */ -#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) -#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) -#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) -#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) -#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) -#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) -#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) -#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) -#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) -#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) - - -/*!< MCU_APB1 */ -#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000) -#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000) -#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000) -#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000) -#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000) -#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000) -#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000) -#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000) -#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000) -#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000) -#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000) -#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000) -#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000) -#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000) -#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000) -#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000) -#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000) -#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000) -#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000) -#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000) -#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000) -#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000) -#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000) -#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000) -#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000) -#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000) -#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000) - -/*!< MCU_APB2 */ -#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000) -#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000) -#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000) -#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000) -#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000) -#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000) -#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000) -#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000) -#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000) +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000) +#define AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000) +#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000) +#define AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000) +#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000) +#define AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000) +#define APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000) +#define APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000) + + +#define MCU_AHB_SRAM AHB_SRAM +#define MCU_AHB_RETRAM AHB_RETRAM +#define MPU_AXI_BUS_MEMORY_BASE AXI_BUS_MEMORY_BASE +#define MCU_APB1_PERIPH_BASE APB1_PERIPH_BASE +#define MCU_APB2_PERIPH_BASE APB2_PERIPH_BASE +#define MCU_AHB2_PERIPH_BASE AHB2_PERIPH_BASE +#define MCU_AHB3_PERIPH_BASE AHB3_PERIPH_BASE +#define MCU_AHB4_PERIPH_BASE AHB4_PERIPH_BASE +#define MCU_APB3_PERIPH_BASE APB3_PERIPH_BASE +#define MPU_AHB5_PERIPH_BASE AHB5_PERIPH_BASE +#define MPU_AHB6_PERIPH_BASE AHB6_PERIPH_BASE +#define MPU_APB4_PERIPH_BASE APB4_PERIPH_BASE +#define MPU_APB5_PERIPH_BASE APB5_PERIPH_BASE + +/*!< APB1 */ +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1_PERIPH_BASE + 0x1000) +#define TIM4_BASE (APB1_PERIPH_BASE + 0x2000) +#define TIM5_BASE (APB1_PERIPH_BASE + 0x3000) +#define TIM6_BASE (APB1_PERIPH_BASE + 0x4000) +#define TIM7_BASE (APB1_PERIPH_BASE + 0x5000) +#define TIM12_BASE (APB1_PERIPH_BASE + 0x6000) +#define TIM13_BASE (APB1_PERIPH_BASE + 0x7000) +#define TIM14_BASE (APB1_PERIPH_BASE + 0x8000) +#define LPTIM1_BASE (APB1_PERIPH_BASE + 0x9000) +#define WWDG1_BASE (APB1_PERIPH_BASE + 0xA000) +#define SPI2_BASE (APB1_PERIPH_BASE + 0xB000) +#define SPI3_BASE (APB1_PERIPH_BASE + 0xC000) +#define SPDIFRX_BASE (APB1_PERIPH_BASE + 0xD000) +#define USART2_BASE (APB1_PERIPH_BASE + 0xE000) +#define USART3_BASE (APB1_PERIPH_BASE + 0xF000) +#define UART4_BASE (APB1_PERIPH_BASE + 0x10000) +#define UART5_BASE (APB1_PERIPH_BASE + 0x11000) +#define I2C1_BASE (APB1_PERIPH_BASE + 0x12000) +#define I2C2_BASE (APB1_PERIPH_BASE + 0x13000) +#define I2C3_BASE (APB1_PERIPH_BASE + 0x14000) +#define I2C5_BASE (APB1_PERIPH_BASE + 0x15000) +#define CEC_BASE (APB1_PERIPH_BASE + 0x16000) +#define DAC1_BASE (APB1_PERIPH_BASE + 0x17000) +#define UART7_BASE (APB1_PERIPH_BASE + 0x18000) +#define UART8_BASE (APB1_PERIPH_BASE + 0x19000) +#define MDIOS_BASE (APB1_PERIPH_BASE + 0x1C000) + +/*!< APB2 */ +#define TIM1_BASE (APB2_PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x3000) +#define SPI1_BASE (APB2_PERIPH_BASE + 0x4000) +#define SPI4_BASE (APB2_PERIPH_BASE + 0x5000) +#define TIM15_BASE (APB2_PERIPH_BASE + 0x6000) +#define TIM16_BASE (APB2_PERIPH_BASE + 0x7000) +#define TIM17_BASE (APB2_PERIPH_BASE + 0x8000) +#define SPI5_BASE (APB2_PERIPH_BASE + 0x9000) +#define SAI1_BASE (APB2_PERIPH_BASE + 0xA000) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000) +#define SAI2_BASE (APB2_PERIPH_BASE + 0xB000) #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000) +#define SAI3_BASE (APB2_PERIPH_BASE + 0xC000) #define SAI3_Block_A_BASE (SAI3_BASE + 0x004) #define SAI3_Block_B_BASE (SAI3_BASE + 0x024) -#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000) +#define DFSDM1_BASE (APB2_PERIPH_BASE + 0xD000) #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) @@ -2883,49 +3033,49 @@ typedef struct #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300) #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380) -#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000) -#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000) -#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100) -#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000) -#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000) - -/*!< MCU_AHB2 */ -#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000) -#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000) -#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000) -#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000) -#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100) -#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300) -#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000) -#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000) -#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000) - - -/*!< MCU_AHB3 */ -#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000) -#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000) -#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000) -#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310) -#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000) -#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000) -#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000) -#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000) - -/*!< MCU_AHB4 */ -#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000) -#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000) -#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000) -#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000) -#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000) -#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000) -#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000) -#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000) -#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000) -#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000) -#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000) -#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000) -#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000) -#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000) +#define FDCAN1_BASE (APB2_PERIPH_BASE + 0xE000) +#define FDCAN2_BASE (APB2_PERIPH_BASE + 0xF000) +#define TTFDCAN1_BASE (APB2_PERIPH_BASE + 0xE100) +#define FDCAN_CCU_BASE (APB2_PERIPH_BASE + 0x10000) +#define SRAMCAN_BASE (APB2_PERIPH_BASE + 0x11000) + +/*!< AHB2 */ +#define DMA1_BASE (AHB2_PERIPH_BASE + 0x0000) +#define DMA2_BASE (AHB2_PERIPH_BASE + 0x1000) +#define DMAMUX1_BASE (AHB2_PERIPH_BASE + 0x2000) +#define ADC1_BASE (AHB2_PERIPH_BASE + 0x3000) +#define ADC2_BASE (AHB2_PERIPH_BASE + 0x3100) +#define ADC12_COMMON_BASE (AHB2_PERIPH_BASE + 0x3300) +#define SDMMC3_BASE (AHB2_PERIPH_BASE + 0x4000) +#define DLYB_SDMMC3_BASE (AHB2_PERIPH_BASE + 0x5000) +#define USBOTG_BASE (AHB2_PERIPH_BASE + 0x1000000) + + +/*!< AHB3 */ +#define HSEM_BASE (AHB3_PERIPH_BASE + 0x0000) +#define IPCC_BASE (AHB3_PERIPH_BASE + 0x1000) +#define HASH2_BASE (AHB3_PERIPH_BASE + 0x2000) +#define HASH2_DIGEST_BASE (AHB3_PERIPH_BASE + 0x2310) +#define RNG2_BASE (AHB3_PERIPH_BASE + 0x3000) +#define CRC2_BASE (AHB3_PERIPH_BASE + 0x4000) +#define CRYP2_BASE (AHB3_PERIPH_BASE + 0x5000) +#define DCMI_BASE (AHB3_PERIPH_BASE + 0x6000) + +/*!< AHB4 */ +#define RCC_BASE (AHB4_PERIPH_BASE + 0x0000) +#define PWR_BASE (AHB4_PERIPH_BASE + 0x1000) +#define GPIOA_BASE (AHB4_PERIPH_BASE + 0x2000) +#define GPIOB_BASE (AHB4_PERIPH_BASE + 0x3000) +#define GPIOC_BASE (AHB4_PERIPH_BASE + 0x4000) +#define GPIOD_BASE (AHB4_PERIPH_BASE + 0x5000) +#define GPIOE_BASE (AHB4_PERIPH_BASE + 0x6000) +#define GPIOF_BASE (AHB4_PERIPH_BASE + 0x7000) +#define GPIOG_BASE (AHB4_PERIPH_BASE + 0x8000) +#define GPIOH_BASE (AHB4_PERIPH_BASE + 0x9000) +#define GPIOI_BASE (AHB4_PERIPH_BASE + 0xA000) +#define GPIOJ_BASE (AHB4_PERIPH_BASE + 0xB000) +#define GPIOK_BASE (AHB4_PERIPH_BASE + 0xC000) +#define AIEC_BASE (AHB4_PERIPH_BASE + 0xD000) #define AIEC_C1_BASE (AIEC_BASE + 0x0080) #define AIEC_C2_BASE (AIEC_BASE + 0x00C0) /* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/ @@ -2934,74 +3084,75 @@ typedef struct #define EXTI_C2_BASE AIEC_C2_BASE -/*!< MCU_APB3 */ -#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000) -#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000) -#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000) -#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000) -#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000) -#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000) -#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000) +/*!< APB3 */ +#define SYSCFG_BASE (APB3_PERIPH_BASE + 0x0000) +#define LPTIM2_BASE (APB3_PERIPH_BASE + 0x1000) +#define LPTIM3_BASE (APB3_PERIPH_BASE + 0x2000) +#define LPTIM4_BASE (APB3_PERIPH_BASE + 0x3000) +#define LPTIM5_BASE (APB3_PERIPH_BASE + 0x4000) +#define VREFBUF_BASE (APB3_PERIPH_BASE + 0x5000) +#define SAI4_BASE (APB3_PERIPH_BASE + 0x7000) #define SAI4_Block_A_BASE (SAI4_BASE + 0x004) #define SAI4_Block_B_BASE (SAI4_BASE + 0x024) -#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000) -#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000) -#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000) +#define DTS_BASE (APB3_PERIPH_BASE + 0x8000) +#define PMB_BASE (APB3_PERIPH_BASE + 0x9000) +#define HDP_BASE (APB3_PERIPH_BASE + 0xA000) -/*!< MCU_AHB4 _APB_Debug */ +/*!< AHB4 _APB_Debug */ #define DBGMCU_BASE ((uint32_t )0x50081000) -/*!< MCU_AHB5 */ -#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000) -#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000) -#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000) -#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310) -#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000) -#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000) +/*!< AHB5 */ +#define BKPSRAM_BASE (AHB5_PERIPH_BASE + 0x0000) +#define CRYP1_BASE (AHB5_PERIPH_BASE + 0x1000) +#define HASH1_BASE (AHB5_PERIPH_BASE + 0x2000) +#define HASH1_DIGEST_BASE (AHB5_PERIPH_BASE + 0x2310) +#define RNG1_BASE (AHB5_PERIPH_BASE + 0x3000) +#define GPIOZ_BASE (AHB5_PERIPH_BASE + 0x4000) /*!< GPV */ /*!< MPU_AHB6 */ -#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000) -#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000) -#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000) -#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000) -#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000) -#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000) -#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000) -#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000) -#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000) -#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000) +#define MDMA_BASE (AHB6_PERIPH_BASE + 0x0000) +#define FMC_R_BASE (AHB6_PERIPH_BASE + 0x2000) +#define QSPI_R_BASE (AHB6_PERIPH_BASE + 0x3000) +#define DLYB_QSPI_BASE (AHB6_PERIPH_BASE + 0x4000) +#define SDMMC1_BASE (AHB6_PERIPH_BASE + 0x5000) +#define DLYB_SDMMC1_BASE (AHB6_PERIPH_BASE + 0x6000) +#define SDMMC2_BASE (AHB6_PERIPH_BASE + 0x7000) +#define DLYB_SDMMC2_BASE (AHB6_PERIPH_BASE + 0x8000) +#define CRC1_BASE (AHB6_PERIPH_BASE + 0x9000) +#define ETH_BASE (AHB6_PERIPH_BASE + 0xA000) #define ETH_MAC_BASE (ETH_BASE) -#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000) -#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000) -#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000) +#define USB1HSFSP2_BASE (AHB6_PERIPH_BASE + 0xC000) +#define USB1HSFSP1_BASE (AHB6_PERIPH_BASE + 0xD000) +#define GPU_BASE (AHB6_PERIPH_BASE + 0x1000000) /*!< MPU_APB4 */ -#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000) -#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000) +#define DSI_BASE (APB4_PERIPH_BASE + 0x0000) +#define LTDC_BASE (APB4_PERIPH_BASE + 0x1000) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000) -#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000) -#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000) -#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000) -#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000) +#define IWDG2_BASE (APB4_PERIPH_BASE + 0x2000) +#define DDRCTRL_BASE (APB4_PERIPH_BASE + 0x3000) +#define DDRPHYC_BASE (APB4_PERIPH_BASE + 0x4000) +#define STGENR_BASE (APB4_PERIPH_BASE + 0x5000) +#define USBPHYC_BASE (APB4_PERIPH_BASE + 0x6000) +#define DDRPERFM_BASE (APB4_PERIPH_BASE + 0x7000) #define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100) #define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200) /*!< MPU_APB5 */ -#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000) -#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000) -#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000) -#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000) -#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000) -#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000) -#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000) -#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000) -#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000) -#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000) -#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000) +#define USART1_BASE (APB5_PERIPH_BASE + 0x0000) +#define SPI6_BASE (APB5_PERIPH_BASE + 0x1000) +#define I2C4_BASE (APB5_PERIPH_BASE + 0x2000) +#define IWDG1_BASE (APB5_PERIPH_BASE + 0x3000) +#define RTC_BASE (APB5_PERIPH_BASE + 0x4000) +#define BSEC_BASE (APB5_PERIPH_BASE + 0x5000) +#define TZC_BASE (APB5_PERIPH_BASE + 0x6000) +#define TZPC_BASE (APB5_PERIPH_BASE + 0x7000) +#define STGENC_BASE (APB5_PERIPH_BASE + 0x8000) +#define I2C6_BASE (APB5_PERIPH_BASE + 0x9000) +#define TAMP_BASE (APB5_PERIPH_BASE + 0xA000) @@ -3039,6 +3190,7 @@ typedef struct #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008) @@ -3065,7 +3217,6 @@ typedef struct #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140) - /*!< FMC Banks registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) @@ -3251,6 +3402,7 @@ typedef struct #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) #define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) @@ -3271,7 +3423,6 @@ typedef struct #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) - #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) @@ -3320,7 +3471,8 @@ typedef struct #define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE) #define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE) -#define DDRC ((DDRC_TypeDef *)DDRC_BASE) +#define DDRCTRL ((DDRCTRL_TypeDef *)DDRCTRL_BASE) +#define DDRPERFM ((DDRPERFM_TypeDef *)DDRPERFM_BASE) #define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) @@ -3330,7 +3482,7 @@ typedef struct #define TZC ((TZC_TypeDef *)TZC_BASE) #define TZPC ((TZPC_TypeDef *)TZPC_BASE) #define STGENC ((STGENC_TypeDef *)STGENC_BASE) - +#define STGENR ((STGENR_TypeDef *)STGENR_BASE) #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) @@ -3699,7 +3851,6 @@ typedef struct #define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - /******************** Bit definition for ADC_SMPR1 register ********************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -3927,6 +4078,7 @@ typedef struct #define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */ #define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */ + /******************** Bit definition for ADC_LTR2 register ********************/ #define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */ #define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ @@ -4200,7 +4352,7 @@ typedef struct #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA_Msk (0xFFFFFFFFU << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ @@ -4471,7 +4623,7 @@ typedef struct /******************** Bit definition for ADC_JDR1 register ********************/ #define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ @@ -4508,7 +4660,7 @@ typedef struct /******************** Bit definition for ADC_JDR2 register ********************/ #define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ @@ -4545,7 +4697,7 @@ typedef struct /******************** Bit definition for ADC_JDR3 register ********************/ #define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ @@ -4582,7 +4734,7 @@ typedef struct /******************** Bit definition for ADC_JDR4 register ********************/ #define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ @@ -4957,6 +5109,97 @@ typedef struct #define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */ #define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_VERR register ******************/ +#define ADC_VERR_MINREV_Pos (0U) +#define ADC_VERR_MINREV_Msk (0xFU << ADC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define ADC_VERR_MINREV ADC_VERR_MINREV_Msk /*!< Minor revision */ +#define ADC_VERR_MINREV_0 (0x1U << ADC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define ADC_VERR_MINREV_1 (0x2U << ADC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define ADC_VERR_MINREV_2 (0x4U << ADC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define ADC_VERR_MINREV_3 (0x8U << ADC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define ADC_VERR_MAJREV_Pos (4U) +#define ADC_VERR_MAJREV_Msk (0xFU << ADC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define ADC_VERR_MAJREV ADC_VERR_MAJREV_Msk /*!< Major revision */ +#define ADC_VERR_MAJREV_0 (0x1U << ADC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define ADC_VERR_MAJREV_1 (0x2U << ADC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define ADC_VERR_MAJREV_2 (0x4U << ADC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define ADC_VERR_MAJREV_3 (0x8U << ADC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for ADC_IPDR register ******************/ +#define ADC_IPDR_ID_Pos (0U) +#define ADC_IPDR_ID_Msk (0xFFFFFFFFU << ADC_IPDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_IPDR_ID ADC_IPDR_ID_Msk /*!< Peripheral identifier */ +#define ADC_IPDR_ID_0 (0x1U << ADC_IPDR_ID_Pos) /*!< 0x00000001 */ +#define ADC_IPDR_ID_1 (0x2U << ADC_IPDR_ID_Pos) /*!< 0x00000002 */ +#define ADC_IPDR_ID_2 (0x4U << ADC_IPDR_ID_Pos) /*!< 0x00000004 */ +#define ADC_IPDR_ID_3 (0x8U << ADC_IPDR_ID_Pos) /*!< 0x00000008 */ +#define ADC_IPDR_ID_4 (0x10U << ADC_IPDR_ID_Pos) /*!< 0x00000010 */ +#define ADC_IPDR_ID_5 (0x20U << ADC_IPDR_ID_Pos) /*!< 0x00000020 */ +#define ADC_IPDR_ID_6 (0x40U << ADC_IPDR_ID_Pos) /*!< 0x00000040 */ +#define ADC_IPDR_ID_7 (0x80U << ADC_IPDR_ID_Pos) /*!< 0x00000080 */ +#define ADC_IPDR_ID_8 (0x100U << ADC_IPDR_ID_Pos) /*!< 0x00000100 */ +#define ADC_IPDR_ID_9 (0x200U << ADC_IPDR_ID_Pos) /*!< 0x00000200 */ +#define ADC_IPDR_ID_10 (0x400U << ADC_IPDR_ID_Pos) /*!< 0x00000400 */ +#define ADC_IPDR_ID_11 (0x800U << ADC_IPDR_ID_Pos) /*!< 0x00000800 */ +#define ADC_IPDR_ID_12 (0x1000U << ADC_IPDR_ID_Pos) /*!< 0x00001000 */ +#define ADC_IPDR_ID_13 (0x2000U << ADC_IPDR_ID_Pos) /*!< 0x00002000 */ +#define ADC_IPDR_ID_14 (0x4000U << ADC_IPDR_ID_Pos) /*!< 0x00004000 */ +#define ADC_IPDR_ID_15 (0x8000U << ADC_IPDR_ID_Pos) /*!< 0x00008000 */ +#define ADC_IPDR_ID_16 (0x10000U << ADC_IPDR_ID_Pos) /*!< 0x00010000 */ +#define ADC_IPDR_ID_17 (0x20000U << ADC_IPDR_ID_Pos) /*!< 0x00020000 */ +#define ADC_IPDR_ID_18 (0x40000U << ADC_IPDR_ID_Pos) /*!< 0x00040000 */ +#define ADC_IPDR_ID_19 (0x80000U << ADC_IPDR_ID_Pos) /*!< 0x00080000 */ +#define ADC_IPDR_ID_20 (0x100000U << ADC_IPDR_ID_Pos) /*!< 0x00100000 */ +#define ADC_IPDR_ID_21 (0x200000U << ADC_IPDR_ID_Pos) /*!< 0x00200000 */ +#define ADC_IPDR_ID_22 (0x400000U << ADC_IPDR_ID_Pos) /*!< 0x00400000 */ +#define ADC_IPDR_ID_23 (0x800000U << ADC_IPDR_ID_Pos) /*!< 0x00800000 */ +#define ADC_IPDR_ID_24 (0x1000000U << ADC_IPDR_ID_Pos) /*!< 0x01000000 */ +#define ADC_IPDR_ID_25 (0x2000000U << ADC_IPDR_ID_Pos) /*!< 0x02000000 */ +#define ADC_IPDR_ID_26 (0x4000000U << ADC_IPDR_ID_Pos) /*!< 0x04000000 */ +#define ADC_IPDR_ID_27 (0x8000000U << ADC_IPDR_ID_Pos) /*!< 0x08000000 */ +#define ADC_IPDR_ID_28 (0x10000000U << ADC_IPDR_ID_Pos) /*!< 0x10000000 */ +#define ADC_IPDR_ID_29 (0x20000000U << ADC_IPDR_ID_Pos) /*!< 0x20000000 */ +#define ADC_IPDR_ID_30 (0x40000000U << ADC_IPDR_ID_Pos) /*!< 0x40000000 */ +#define ADC_IPDR_ID_31 (0x80000000U << ADC_IPDR_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for ADC_SIDR register ******************/ +#define ADC_SIDR_SID_Pos (0U) +#define ADC_SIDR_SID_Msk (0xFFFFFFFFU << ADC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define ADC_SIDR_SID ADC_SIDR_SID_Msk /*!< Size Identification */ +#define ADC_SIDR_SID_0 (0x1U << ADC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define ADC_SIDR_SID_1 (0x2U << ADC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define ADC_SIDR_SID_2 (0x4U << ADC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define ADC_SIDR_SID_3 (0x8U << ADC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define ADC_SIDR_SID_4 (0x10U << ADC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define ADC_SIDR_SID_5 (0x20U << ADC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define ADC_SIDR_SID_6 (0x40U << ADC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define ADC_SIDR_SID_7 (0x80U << ADC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define ADC_SIDR_SID_8 (0x100U << ADC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define ADC_SIDR_SID_9 (0x200U << ADC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define ADC_SIDR_SID_10 (0x400U << ADC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define ADC_SIDR_SID_11 (0x800U << ADC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define ADC_SIDR_SID_12 (0x1000U << ADC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define ADC_SIDR_SID_13 (0x2000U << ADC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define ADC_SIDR_SID_14 (0x4000U << ADC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define ADC_SIDR_SID_15 (0x8000U << ADC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define ADC_SIDR_SID_16 (0x10000U << ADC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define ADC_SIDR_SID_17 (0x20000U << ADC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define ADC_SIDR_SID_18 (0x40000U << ADC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define ADC_SIDR_SID_19 (0x80000U << ADC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define ADC_SIDR_SID_20 (0x100000U << ADC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define ADC_SIDR_SID_21 (0x200000U << ADC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define ADC_SIDR_SID_22 (0x400000U << ADC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define ADC_SIDR_SID_23 (0x800000U << ADC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define ADC_SIDR_SID_24 (0x1000000U << ADC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define ADC_SIDR_SID_25 (0x2000000U << ADC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define ADC_SIDR_SID_26 (0x4000000U << ADC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define ADC_SIDR_SID_27 (0x8000000U << ADC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define ADC_SIDR_SID_28 (0x10000000U << ADC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define ADC_SIDR_SID_29 (0x20000000U << ADC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define ADC_SIDR_SID_30 (0x40000000U << ADC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define ADC_SIDR_SID_31 (0x80000000U << ADC_SIDR_SID_Pos) /*!< 0x80000000 */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -7429,6 +7672,4571 @@ typedef struct #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/******************************************************************************/ +/* */ +/* DDRCTRL block description (DDRCTRL) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRCTRL_MSTR register *****************/ +#define DDRCTRL_MSTR_DDR3_Pos (0U) +#define DDRCTRL_MSTR_DDR3_Msk (0x1U << DDRCTRL_MSTR_DDR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MSTR_DDR3 DDRCTRL_MSTR_DDR3_Msk /*!< Selects DDR3 SDRAM */ +#define DDRCTRL_MSTR_LPDDR2_Pos (2U) +#define DDRCTRL_MSTR_LPDDR2_Msk (0x1U << DDRCTRL_MSTR_LPDDR2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MSTR_LPDDR2 DDRCTRL_MSTR_LPDDR2_Msk /*!< Selects LPDDR2 SDRAM */ +#define DDRCTRL_MSTR_LPDDR3_Pos (3U) +#define DDRCTRL_MSTR_LPDDR3_Msk (0x1U << DDRCTRL_MSTR_LPDDR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MSTR_LPDDR3 DDRCTRL_MSTR_LPDDR3_Msk /*!< Selects LPDDR3 SDRAM */ +#define DDRCTRL_MSTR_BURSTCHOP_Pos (9U) +#define DDRCTRL_MSTR_BURSTCHOP_Msk (0x1U << DDRCTRL_MSTR_BURSTCHOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MSTR_BURSTCHOP DDRCTRL_MSTR_BURSTCHOP_Msk /*!< When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full bus width mode (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. The burst-chop for writes is exercised only if partial writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos (10U) +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk (0x1U << DDRCTRL_MSTR_EN_2T_TIMING_MODE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MSTR_EN_2T_TIMING_MODE DDRCTRL_MSTR_EN_2T_TIMING_MODE_Msk /*!< If 1, then the DDRCTRL uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. The chip select is asserted on the second cycle of the command */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos (12U) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk (0x3U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00003000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH DDRCTRL_MSTR_DATA_BUS_WIDTH_Msk /*!< Selects proportion of DQ bus width that is used by the SDRAM */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_0 (0x1U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_1 (0x2U << DDRCTRL_MSTR_DATA_BUS_WIDTH_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE_Pos (15U) +#define DDRCTRL_MSTR_DLL_OFF_MODE_Msk (0x1U << DDRCTRL_MSTR_DLL_OFF_MODE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MSTR_DLL_OFF_MODE DDRCTRL_MSTR_DLL_OFF_MODE_Msk /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low frequency operation. */ +#define DDRCTRL_MSTR_BURST_RDWR_Pos (16U) +#define DDRCTRL_MSTR_BURST_RDWR_Msk (0xFU << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_MSTR_BURST_RDWR DDRCTRL_MSTR_BURST_RDWR_Msk /*!< SDRAM burst length used: */ +#define DDRCTRL_MSTR_BURST_RDWR_0 (0x1U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_MSTR_BURST_RDWR_1 (0x2U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_MSTR_BURST_RDWR_2 (0x4U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_MSTR_BURST_RDWR_3 (0x8U << DDRCTRL_MSTR_BURST_RDWR_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for DDRCTRL_STAT register *****************/ +#define DDRCTRL_STAT_OPERATING_MODE_Pos (0U) +#define DDRCTRL_STAT_OPERATING_MODE_Msk (0x7U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000007 */ +#define DDRCTRL_STAT_OPERATING_MODE DDRCTRL_STAT_OPERATING_MODE_Msk /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. */ +#define DDRCTRL_STAT_OPERATING_MODE_0 (0x1U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_STAT_OPERATING_MODE_1 (0x2U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_STAT_OPERATING_MODE_2 (0x4U << DDRCTRL_STAT_OPERATING_MODE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_STAT_SELFREF_TYPE_Pos (4U) +#define DDRCTRL_STAT_SELFREF_TYPE_Msk (0x3U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000030 */ +#define DDRCTRL_STAT_SELFREF_TYPE DDRCTRL_STAT_SELFREF_TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it was under Automatic Self Refresh control only or not. */ +#define DDRCTRL_STAT_SELFREF_TYPE_0 (0x1U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_STAT_SELFREF_TYPE_1 (0x2U << DDRCTRL_STAT_SELFREF_TYPE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos (12U) +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk (0x1U << DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Pos) /*!< 0x00001000 */ +#define DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY DDRCTRL_STAT_SELFREF_CAM_NOT_EMPTY_Msk /*!< Self refresh with CAMs not empty. Set to 1 when Self Refresh is entered but CAMs are not drained. Cleared after exiting Self Refresh. */ + +/*************** Bit definition for DDRCTRL_MRCTRL0 register ****************/ +#define DDRCTRL_MRCTRL0_MR_TYPE_Pos (0U) +#define DDRCTRL_MRCTRL0_MR_TYPE_Msk (0x1U << DDRCTRL_MRCTRL0_MR_TYPE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL0_MR_TYPE DDRCTRL_MRCTRL0_MR_TYPE_Msk /*!< Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. */ +#define DDRCTRL_MRCTRL0_MR_RANK_Pos (4U) +#define DDRCTRL_MRCTRL0_MR_RANK_Msk (0x1U << DDRCTRL_MRCTRL0_MR_RANK_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL0_MR_RANK DDRCTRL_MRCTRL0_MR_RANK_Msk /*!< Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_Pos (12U) +#define DDRCTRL_MRCTRL0_MR_ADDR_Msk (0xFU << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR DDRCTRL_MRCTRL0_MR_ADDR_Msk /*!< Address of the mode register that is to be written to. */ +#define DDRCTRL_MRCTRL0_MR_ADDR_0 (0x1U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_1 (0x2U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_2 (0x4U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL0_MR_ADDR_3 (0x8U << DDRCTRL_MRCTRL0_MR_ADDR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_MRCTRL0_MR_WR_Pos (31U) +#define DDRCTRL_MRCTRL0_MR_WR_Msk (0x1U << DDRCTRL_MRCTRL0_MR_WR_Pos) /*!< 0x80000000 */ +#define DDRCTRL_MRCTRL0_MR_WR DDRCTRL_MRCTRL0_MR_WR_Msk /*!< Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRCTRL automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. */ + +/*************** Bit definition for DDRCTRL_MRCTRL1 register ****************/ +#define DDRCTRL_MRCTRL1_MR_DATA_Pos (0U) +#define DDRCTRL_MRCTRL1_MR_DATA_Msk (0xFFFFU << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_MRCTRL1_MR_DATA DDRCTRL_MRCTRL1_MR_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. */ +#define DDRCTRL_MRCTRL1_MR_DATA_0 (0x1U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRCTRL1_MR_DATA_1 (0x2U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000002 */ +#define DDRCTRL_MRCTRL1_MR_DATA_2 (0x4U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000004 */ +#define DDRCTRL_MRCTRL1_MR_DATA_3 (0x8U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000008 */ +#define DDRCTRL_MRCTRL1_MR_DATA_4 (0x10U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000010 */ +#define DDRCTRL_MRCTRL1_MR_DATA_5 (0x20U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000020 */ +#define DDRCTRL_MRCTRL1_MR_DATA_6 (0x40U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000040 */ +#define DDRCTRL_MRCTRL1_MR_DATA_7 (0x80U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000080 */ +#define DDRCTRL_MRCTRL1_MR_DATA_8 (0x100U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_MRCTRL1_MR_DATA_9 (0x200U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_MRCTRL1_MR_DATA_10 (0x400U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_MRCTRL1_MR_DATA_11 (0x800U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_MRCTRL1_MR_DATA_12 (0x1000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_13 (0x2000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_14 (0x4000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00004000 */ +#define DDRCTRL_MRCTRL1_MR_DATA_15 (0x8000U << DDRCTRL_MRCTRL1_MR_DATA_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_MRSTAT register ****************/ +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Pos (0U) +#define DDRCTRL_MRSTAT_MR_WR_BUSY_Msk (0x1U << DDRCTRL_MRSTAT_MR_WR_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_MRSTAT_MR_WR_BUSY DDRCTRL_MRSTAT_MR_WR_BUSY_Msk /*!< The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when \qMRSTAT.mr_wr_busy\q is high. */ + +/*************** Bit definition for DDRCTRL_DERATEEN register ***************/ +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Pos (0U) +#define DDRCTRL_DERATEEN_DERATE_ENABLE_Msk (0x1U << DDRCTRL_DERATEEN_DERATE_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEEN_DERATE_ENABLE DDRCTRL_DERATEEN_DERATE_ENABLE_Msk /*!< Enables derating */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_Pos (1U) +#define DDRCTRL_DERATEEN_DERATE_VALUE_Msk (0x3U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000006 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE DDRCTRL_DERATEEN_DERATE_VALUE_Msk /*!< Derate value */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEEN_DERATE_VALUE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_VALUE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_Pos (4U) +#define DDRCTRL_DERATEEN_DERATE_BYTE_Msk (0xFU << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE DDRCTRL_DERATEEN_DERATE_BYTE_Msk /*!< Derate byte */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_0 (0x1U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_1 (0x2U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_2 (0x4U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEEN_DERATE_BYTE_3 (0x8U << DDRCTRL_DERATEEN_DERATE_BYTE_Pos) /*!< 0x00000080 */ + +/************** Bit definition for DDRCTRL_DERATEINT register ***************/ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos (0U) +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk (0xFFFFFFFFU << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0xFFFFFFFF */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Msk /*!< Interval between two MR4 reads, used to derate the timing parameters. */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_0 (0x1U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_1 (0x2U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_2 (0x4U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_3 (0x8U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_4 (0x10U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_5 (0x20U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_6 (0x40U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_7 (0x80U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_8 (0x100U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_9 (0x200U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_10 (0x400U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_11 (0x800U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_12 (0x1000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_13 (0x2000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_14 (0x4000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_15 (0x8000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_16 (0x10000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_17 (0x20000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_18 (0x40000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_19 (0x80000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_20 (0x100000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_21 (0x200000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_22 (0x400000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_23 (0x800000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_24 (0x1000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_25 (0x2000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_26 (0x4000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_27 (0x8000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_28 (0x10000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_29 (0x20000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_30 (0x40000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DERATEINT_MR4_READ_INTERVAL_31 (0x80000000U << DDRCTRL_DERATEINT_MR4_READ_INTERVAL_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_PWRCTL register ****************/ +#define DDRCTRL_PWRCTL_SELFREF_EN_Pos (0U) +#define DDRCTRL_PWRCTL_SELFREF_EN_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRCTL_SELFREF_EN DDRCTRL_PWRCTL_SELFREF_EN_Msk /*!< If true then the DDRCTRL puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation. */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Pos (1U) +#define DDRCTRL_PWRCTL_POWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_POWERDOWN_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRCTL_POWERDOWN_EN DDRCTRL_PWRCTL_POWERDOWN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos (2U) +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk (0x1U << DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN DDRCTRL_PWRCTL_DEEPPOWERDOWN_EN_Msk /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the transaction store is empty. */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos (3U) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk (0x1U << DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk /*!< Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. */ +#define DDRCTRL_PWRCTL_SELFREF_SW_Pos (5U) +#define DDRCTRL_PWRCTL_SELFREF_SW_Msk (0x1U << DDRCTRL_PWRCTL_SELFREF_SW_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PWRCTL_SELFREF_SW DDRCTRL_PWRCTL_SELFREF_SW_Msk /*!< A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos (7U) +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk (0x1U << DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF DDRCTRL_PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */ + +/**************** Bit definition for DDRCTRL_PWRTMG register ****************/ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos (0U) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk (0x1FU << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x0000001F */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32 DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_POWERDOWN_TO_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_Pos (8U) +#define DDRCTRL_PWRTMG_T_DPD_X4096_Msk (0xFFU << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_0 (0x1U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_1 (0x2U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_2 (0x4U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_3 (0x8U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_4 (0x10U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_5 (0x20U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_6 (0x40U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PWRTMG_T_DPD_X4096_7 (0x80U << DDRCTRL_PWRTMG_T_DPD_X4096_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos (16U) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk (0xFFU << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32 DDRCTRL_PWRTMG_SELFREF_TO_X32_Msk /*!< After this many clocks of the DDRC command channel being idle the DDRCTRL automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 (0x1U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_1 (0x2U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_2 (0x4U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_3 (0x8U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_4 (0x10U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_5 (0x20U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_6 (0x40U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_7 (0x80U << DDRCTRL_PWRTMG_SELFREF_TO_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_HWLPCTL register ****************/ +#define DDRCTRL_HWLPCTL_HW_LP_EN_Pos (0U) +#define DDRCTRL_HWLPCTL_HW_LP_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_HWLPCTL_HW_LP_EN DDRCTRL_HWLPCTL_HW_LP_EN_Msk /*!< Enable for hardware low power interface. */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos (1U) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk (0x1U << DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk /*!< When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of Self-Refresh that is caused by Hardware Low power interface and/or software (PWRCTL.selfref_sw). */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos (16U) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk (0xFFFU << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32 DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Msk /*!< Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_0 (0x1U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_1 (0x2U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_2 (0x4U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_3 (0x8U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_4 (0x10U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_5 (0x20U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_6 (0x40U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_7 (0x80U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_8 (0x100U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_9 (0x200U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_10 (0x400U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_11 (0x800U << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL0 register ***************/ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos (2U) +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHCTL0_PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos (4U) +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x000001F0 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST DDRCTRL_RFSHCTL0_REFRESH_BURST_Msk /*!< The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHCTL0_REFRESH_BURST_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_BURST_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos (12U) +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk (0x1FU << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x0001F000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32 DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Msk /*!< If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRCTRL. */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_TO_X32_4 (0x10U << DDRCTRL_RFSHCTL0_REFRESH_TO_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos (20U) +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk (0xFU << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Msk /*!< Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32. Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1). */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_0 (0x1U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_1 (0x2U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_2 (0x4U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHCTL0_REFRESH_MARGIN_3 (0x8U << DDRCTRL_RFSHCTL0_REFRESH_MARGIN_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_RFSHCTL3 register ***************/ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos (0U) +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk (0x1U << DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh. */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos (1U) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk (0x1U << DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL_Msk /*!< Toggles this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. */ + +/*************** Bit definition for DDRCTRL_RFSHTMG register ****************/ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Pos (0U) +#define DDRCTRL_RFSHTMG_T_RFC_MIN_Msk (0x3FFU << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN DDRCTRL_RFSHTMG_T_RFC_MIN_Msk /*!< tRFC (min): Minimum time from refresh to refresh or activate. */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_RFSHTMG_T_RFC_MIN_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos (15U) +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk (0x1U << DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Pos) /*!< 0x00008000 */ +#define DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN DDRCTRL_RFSHTMG_LPDDR3_TREFBW_EN_Msk /*!< Used only when LPDDR3 memory type is connected. Should only be changed when DDRCTRL is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos (16U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk (0xFFFU << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x0FFF0000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32 DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Msk /*!< tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_0 (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_1 (0x2U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_2 (0x4U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_3 (0x8U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_4 (0x10U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_5 (0x20U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_6 (0x40U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_7 (0x80U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x00800000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_8 (0x100U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x01000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_9 (0x200U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x02000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_10 (0x400U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x04000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_11 (0x800U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_Pos) /*!< 0x08000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos (31U) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk (0x1U << DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Pos) /*!< 0x80000000 */ +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL DDRCTRL_RFSHTMG_T_RFC_NOM_X1_SEL_Msk /*!< Specifies whether the t_rfc_nom_x1_x32 register value is x1 or x32. */ + +/************** Bit definition for DDRCTRL_CRCPARCTL0 register **************/ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos (0U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_Msk /*!< Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos (1U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_Msk /*!< Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos (2U) +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk (0x1U << DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR DDRCTRL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_Msk /*!< DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit, clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the DDRCTRL automatically clears this bit. */ + +/************** Bit definition for DDRCTRL_CRCPARSTAT register **************/ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos (0U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk (0xFFFFU << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Msk /*!< DFI alert error count. */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_0 (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_1 (0x2U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_2 (0x4U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_3 (0x8U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_4 (0x10U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_5 (0x20U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_6 (0x40U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000040 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_7 (0x80U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000080 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_8 (0x100U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000100 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_9 (0x200U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000200 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_10 (0x400U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000400 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_11 (0x800U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00000800 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_12 (0x1000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00001000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_13 (0x2000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00002000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_14 (0x4000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00004000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_15 (0x8000U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_CNT_Pos) /*!< 0x00008000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos (16U) +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk (0x1U << DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Pos) /*!< 0x00010000 */ +#define DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT DDRCTRL_CRCPARSTAT_DFI_ALERT_ERR_INT_Msk /*!< DFI alert error interrupt. */ + +/**************** Bit definition for DDRCTRL_INIT0 register *****************/ +#define DDRCTRL_INIT0_PRE_CKE_X1024_Pos (0U) +#define DDRCTRL_INIT0_PRE_CKE_X1024_Msk (0xFFFU << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_INIT0_PRE_CKE_X1024 DDRCTRL_INIT0_PRE_CKE_X1024_Msk /*!< Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_10 (0x400U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT0_PRE_CKE_X1024_11 (0x800U << DDRCTRL_INIT0_PRE_CKE_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_Pos (16U) +#define DDRCTRL_INIT0_POST_CKE_X1024_Msk (0x3FFU << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024 DDRCTRL_INIT0_POST_CKE_X1024_Msk /*!< Cycles to wait after driving CKE high to start the SDRAM initialization sequence. */ +#define DDRCTRL_INIT0_POST_CKE_X1024_0 (0x1U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_1 (0x2U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_2 (0x4U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_3 (0x8U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_4 (0x10U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_5 (0x20U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_6 (0x40U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_7 (0x80U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_8 (0x100U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT0_POST_CKE_X1024_9 (0x200U << DDRCTRL_INIT0_POST_CKE_X1024_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos (30U) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk (0x3U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0xC0000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT DDRCTRL_INIT0_SKIP_DRAM_INIT_Msk /*!< If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_0 (0x1U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_1 (0x2U << DDRCTRL_INIT0_SKIP_DRAM_INIT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT1 register *****************/ +#define DDRCTRL_INIT1_PRE_OCD_X32_Pos (0U) +#define DDRCTRL_INIT1_PRE_OCD_X32_Msk (0xFU << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT1_PRE_OCD_X32 DDRCTRL_INIT1_PRE_OCD_X32_Msk /*!< Wait period before driving the OCD complete command to SDRAM. */ +#define DDRCTRL_INIT1_PRE_OCD_X32_0 (0x1U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_1 (0x2U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_2 (0x4U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT1_PRE_OCD_X32_3 (0x8U << DDRCTRL_INIT1_PRE_OCD_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos (16U) +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk (0x1FFU << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01FF0000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024 DDRCTRL_INIT1_DRAM_RSTN_X1024_Msk /*!< Number of cycles to assert SDRAM reset signal during init sequence. */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_0 (0x1U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_1 (0x2U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_2 (0x4U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_3 (0x8U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_4 (0x10U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_5 (0x20U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_6 (0x40U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_7 (0x80U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT1_DRAM_RSTN_X1024_8 (0x100U << DDRCTRL_INIT1_DRAM_RSTN_X1024_Pos) /*!< 0x01000000 */ + +/**************** Bit definition for DDRCTRL_INIT2 register *****************/ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos (0U) +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk (0xFU << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1 DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Msk /*!< Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_0 (0x1U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_1 (0x2U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_2 (0x4U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_3 (0x8U << DDRCTRL_INIT2_MIN_STABLE_CLOCK_X1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos (8U) +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk (0xFFU << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x0000FF00 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32 DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Msk /*!< Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_0 (0x1U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_1 (0x2U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_2 (0x4U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_3 (0x8U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_4 (0x10U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_5 (0x20U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_6 (0x40U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_7 (0x80U << DDRCTRL_INIT2_IDLE_AFTER_RESET_X32_Pos) /*!< 0x00008000 */ + +/**************** Bit definition for DDRCTRL_INIT3 register *****************/ +#define DDRCTRL_INIT3_EMR_Pos (0U) +#define DDRCTRL_INIT3_EMR_Msk (0xFFFFU << DDRCTRL_INIT3_EMR_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT3_EMR DDRCTRL_INIT3_EMR_Msk /*!< DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The DDRCTRL sets those bits appropriately. */ +#define DDRCTRL_INIT3_EMR_0 (0x1U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT3_EMR_1 (0x2U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT3_EMR_2 (0x4U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT3_EMR_3 (0x8U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT3_EMR_4 (0x10U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT3_EMR_5 (0x20U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT3_EMR_6 (0x40U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT3_EMR_7 (0x80U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT3_EMR_8 (0x100U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT3_EMR_9 (0x200U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT3_EMR_10 (0x400U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT3_EMR_11 (0x800U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT3_EMR_12 (0x1000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT3_EMR_13 (0x2000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT3_EMR_14 (0x4000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT3_EMR_15 (0x8000U << DDRCTRL_INIT3_EMR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT3_MR_Pos (16U) +#define DDRCTRL_INIT3_MR_Msk (0xFFFFU << DDRCTRL_INIT3_MR_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT3_MR DDRCTRL_INIT3_MR_Msk /*!< DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The DDRCTRL sets this bit appropriately. */ +#define DDRCTRL_INIT3_MR_0 (0x1U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT3_MR_1 (0x2U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT3_MR_2 (0x4U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT3_MR_3 (0x8U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT3_MR_4 (0x10U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT3_MR_5 (0x20U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT3_MR_6 (0x40U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT3_MR_7 (0x80U << DDRCTRL_INIT3_MR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT3_MR_8 (0x100U << DDRCTRL_INIT3_MR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT3_MR_9 (0x200U << DDRCTRL_INIT3_MR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT3_MR_10 (0x400U << DDRCTRL_INIT3_MR_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT3_MR_11 (0x800U << DDRCTRL_INIT3_MR_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT3_MR_12 (0x1000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT3_MR_13 (0x2000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT3_MR_14 (0x4000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT3_MR_15 (0x8000U << DDRCTRL_INIT3_MR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT4 register *****************/ +#define DDRCTRL_INIT4_EMR3_Pos (0U) +#define DDRCTRL_INIT4_EMR3_Msk (0xFFFFU << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_INIT4_EMR3 DDRCTRL_INIT4_EMR3_Msk /*!< DDR2: Value to write to EMR3 register. */ +#define DDRCTRL_INIT4_EMR3_0 (0x1U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT4_EMR3_1 (0x2U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT4_EMR3_2 (0x4U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT4_EMR3_3 (0x8U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT4_EMR3_4 (0x10U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT4_EMR3_5 (0x20U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT4_EMR3_6 (0x40U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT4_EMR3_7 (0x80U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT4_EMR3_8 (0x100U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT4_EMR3_9 (0x200U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT4_EMR3_10 (0x400U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_INIT4_EMR3_11 (0x800U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_INIT4_EMR3_12 (0x1000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00001000 */ +#define DDRCTRL_INIT4_EMR3_13 (0x2000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00002000 */ +#define DDRCTRL_INIT4_EMR3_14 (0x4000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00004000 */ +#define DDRCTRL_INIT4_EMR3_15 (0x8000U << DDRCTRL_INIT4_EMR3_Pos) /*!< 0x00008000 */ +#define DDRCTRL_INIT4_EMR2_Pos (16U) +#define DDRCTRL_INIT4_EMR2_Msk (0xFFFFU << DDRCTRL_INIT4_EMR2_Pos) /*!< 0xFFFF0000 */ +#define DDRCTRL_INIT4_EMR2 DDRCTRL_INIT4_EMR2_Msk /*!< DDR2: Value to write to EMR2 register. */ +#define DDRCTRL_INIT4_EMR2_0 (0x1U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT4_EMR2_1 (0x2U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT4_EMR2_2 (0x4U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT4_EMR2_3 (0x8U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT4_EMR2_4 (0x10U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT4_EMR2_5 (0x20U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT4_EMR2_6 (0x40U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT4_EMR2_7 (0x80U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_INIT4_EMR2_8 (0x100U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_INIT4_EMR2_9 (0x200U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_INIT4_EMR2_10 (0x400U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x04000000 */ +#define DDRCTRL_INIT4_EMR2_11 (0x800U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x08000000 */ +#define DDRCTRL_INIT4_EMR2_12 (0x1000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x10000000 */ +#define DDRCTRL_INIT4_EMR2_13 (0x2000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x20000000 */ +#define DDRCTRL_INIT4_EMR2_14 (0x4000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x40000000 */ +#define DDRCTRL_INIT4_EMR2_15 (0x8000U << DDRCTRL_INIT4_EMR2_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRCTRL_INIT5 register *****************/ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos (0U) +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk (0x3FFU << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x000003FF */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024 DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Msk /*!< Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_0 (0x1U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_1 (0x2U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_2 (0x4U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_3 (0x8U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_4 (0x10U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_5 (0x20U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_6 (0x40U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_7 (0x80U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_8 (0x100U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_9 (0x200U << DDRCTRL_INIT5_MAX_AUTO_INIT_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos (16U) +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk (0xFFU << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32 DDRCTRL_INIT5_DEV_ZQINIT_X32_Msk /*!< ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_0 (0x1U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00010000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_1 (0x2U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00020000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_2 (0x4U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00040000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_3 (0x8U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00080000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_4 (0x10U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00100000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_5 (0x20U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00200000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_6 (0x40U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00400000 */ +#define DDRCTRL_INIT5_DEV_ZQINIT_X32_7 (0x80U << DDRCTRL_INIT5_DEV_ZQINIT_X32_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DIMMCTL register ****************/ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos (0U) +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN DDRCTRL_DIMMCTL_DIMM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos (1U) +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk (0x1U << DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN DDRCTRL_DIMMCTL_DIMM_ADDR_MIRR_EN_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). */ + +/*************** Bit definition for DDRCTRL_DRAMTMG0 register ***************/ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos (0U) +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN DDRCTRL_DRAMTMG0_T_RAS_MIN_Msk /*!< tRAS(min): Minimum time between activate and precharge to the same bank. */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MIN_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos (8U) +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk (0x7FU << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX DDRCTRL_DRAMTMG0_T_RAS_MAX_Msk /*!< tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_0 (0x1U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_1 (0x2U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_2 (0x4U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_3 (0x8U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_4 (0x10U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_5 (0x20U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG0_T_RAS_MAX_6 (0x40U << DDRCTRL_DRAMTMG0_T_RAS_MAX_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_Pos (16U) +#define DDRCTRL_DRAMTMG0_T_FAW_Msk (0x3FU << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG0_T_FAW DDRCTRL_DRAMTMG0_T_FAW_Msk /*!< tFAW Valid only when 8 or more banks(or banks x bank groups) are present. */ +#define DDRCTRL_DRAMTMG0_T_FAW_0 (0x1U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_1 (0x2U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_2 (0x4U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_3 (0x8U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_4 (0x10U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG0_T_FAW_5 (0x20U << DDRCTRL_DRAMTMG0_T_FAW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_Pos (24U) +#define DDRCTRL_DRAMTMG0_WR2PRE_Msk (0x7FU << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE DDRCTRL_DRAMTMG0_WR2PRE_Msk /*!< Minimum time between write and precharge to same bank. */ +#define DDRCTRL_DRAMTMG0_WR2PRE_0 (0x1U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_1 (0x2U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_2 (0x4U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_3 (0x8U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_4 (0x10U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_5 (0x20U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DRAMTMG0_WR2PRE_6 (0x40U << DDRCTRL_DRAMTMG0_WR2PRE_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG1 register ***************/ +#define DDRCTRL_DRAMTMG1_T_RC_Pos (0U) +#define DDRCTRL_DRAMTMG1_T_RC_Msk (0x7FU << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG1_T_RC DDRCTRL_DRAMTMG1_T_RC_Msk /*!< tRC: Minimum time between activates to same bank. */ +#define DDRCTRL_DRAMTMG1_T_RC_0 (0x1U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG1_T_RC_1 (0x2U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG1_T_RC_2 (0x4U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG1_T_RC_3 (0x8U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG1_T_RC_4 (0x10U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG1_T_RC_5 (0x20U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG1_T_RC_6 (0x40U << DDRCTRL_DRAMTMG1_T_RC_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_Pos (8U) +#define DDRCTRL_DRAMTMG1_RD2PRE_Msk (0x3FU << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG1_RD2PRE DDRCTRL_DRAMTMG1_RD2PRE_Msk /*!< tRTP: Minimum time from read to precharge of same bank. */ +#define DDRCTRL_DRAMTMG1_RD2PRE_0 (0x1U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_1 (0x2U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_2 (0x4U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_3 (0x8U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_4 (0x10U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG1_RD2PRE_5 (0x20U << DDRCTRL_DRAMTMG1_RD2PRE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG1_T_XP_Pos (16U) +#define DDRCTRL_DRAMTMG1_T_XP_Msk (0x1FU << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DRAMTMG1_T_XP DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. */ +#define DDRCTRL_DRAMTMG1_T_XP_0 (0x1U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG1_T_XP_1 (0x2U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG1_T_XP_2 (0x4U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG1_T_XP_3 (0x8U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG1_T_XP_4 (0x10U << DDRCTRL_DRAMTMG1_T_XP_Pos) /*!< 0x00100000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG2 register ***************/ +#define DDRCTRL_DRAMTMG2_WR2RD_Pos (0U) +#define DDRCTRL_DRAMTMG2_WR2RD_Msk (0x3FU << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DRAMTMG2_WR2RD DDRCTRL_DRAMTMG2_WR2RD_Msk /*!< DDR4: CWL + PL + BL/2 + tWTR_L */ +#define DDRCTRL_DRAMTMG2_WR2RD_0 (0x1U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG2_WR2RD_1 (0x2U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG2_WR2RD_2 (0x4U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG2_WR2RD_3 (0x8U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG2_WR2RD_4 (0x10U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG2_WR2RD_5 (0x20U << DDRCTRL_DRAMTMG2_WR2RD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG2_RD2WR_Pos (8U) +#define DDRCTRL_DRAMTMG2_RD2WR_Msk (0x3FU << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG2_RD2WR DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */ +#define DDRCTRL_DRAMTMG2_RD2WR_0 (0x1U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG2_RD2WR_1 (0x2U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG2_RD2WR_2 (0x4U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG2_RD2WR_3 (0x8U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG2_RD2WR_4 (0x10U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG2_RD2WR_5 (0x20U << DDRCTRL_DRAMTMG2_RD2WR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Pos (16U) +#define DDRCTRL_DRAMTMG2_READ_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY DDRCTRL_DRAMTMG2_READ_LATENCY_Msk /*!< Set to RL */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG2_READ_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_READ_LATENCY_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos (24U) +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk (0x3FU << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x3F000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY DDRCTRL_DRAMTMG2_WRITE_LATENCY_Msk /*!< Set to WL */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_0 (0x1U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_1 (0x2U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_2 (0x4U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_3 (0x8U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_4 (0x10U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG2_WRITE_LATENCY_5 (0x20U << DDRCTRL_DRAMTMG2_WRITE_LATENCY_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG3 register ***************/ +#define DDRCTRL_DRAMTMG3_T_MOD_Pos (0U) +#define DDRCTRL_DRAMTMG3_T_MOD_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DRAMTMG3_T_MOD DDRCTRL_DRAMTMG3_T_MOD_Msk /*!< tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */ +#define DDRCTRL_DRAMTMG3_T_MOD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG3_T_MOD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG3_T_MOD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG3_T_MOD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG3_T_MOD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG3_T_MOD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG3_T_MOD_6 (0x40U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG3_T_MOD_7 (0x80U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG3_T_MOD_8 (0x100U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG3_T_MOD_9 (0x200U << DDRCTRL_DRAMTMG3_T_MOD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG3_T_MRD_Pos (12U) +#define DDRCTRL_DRAMTMG3_T_MRD_Msk (0x3FU << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x0003F000 */ +#define DDRCTRL_DRAMTMG3_T_MRD DDRCTRL_DRAMTMG3_T_MRD_Msk /*!< tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: */ +#define DDRCTRL_DRAMTMG3_T_MRD_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG3_T_MRD_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_Pos (20U) +#define DDRCTRL_DRAMTMG3_T_MRW_Msk (0x3FFU << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_DRAMTMG3_T_MRW DDRCTRL_DRAMTMG3_T_MRW_Msk /*!< Time to wait after a mode register write or read (MRW or MRR). */ +#define DDRCTRL_DRAMTMG3_T_MRW_0 (0x1U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_1 (0x2U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_2 (0x4U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_3 (0x8U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_4 (0x10U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_5 (0x20U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_6 (0x40U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_7 (0x80U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_8 (0x100U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DRAMTMG3_T_MRW_9 (0x200U << DDRCTRL_DRAMTMG3_T_MRW_Pos) /*!< 0x20000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG4 register ***************/ +#define DDRCTRL_DRAMTMG4_T_RP_Pos (0U) +#define DDRCTRL_DRAMTMG4_T_RP_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG4_T_RP DDRCTRL_DRAMTMG4_T_RP_Msk /*!< tRP: Minimum time from precharge to activate of same bank. */ +#define DDRCTRL_DRAMTMG4_T_RP_0 (0x1U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG4_T_RP_1 (0x2U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG4_T_RP_2 (0x4U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG4_T_RP_3 (0x8U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG4_T_RP_4 (0x10U << DDRCTRL_DRAMTMG4_T_RP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG4_T_RRD_Pos (8U) +#define DDRCTRL_DRAMTMG4_T_RRD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG4_T_RRD DDRCTRL_DRAMTMG4_T_RRD_Msk /*!< DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_RRD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG4_T_RRD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG4_T_RRD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG4_T_RRD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RRD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG4_T_CCD_Pos (16U) +#define DDRCTRL_DRAMTMG4_T_CCD_Msk (0xFU << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG4_T_CCD DDRCTRL_DRAMTMG4_T_CCD_Msk /*!< DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. */ +#define DDRCTRL_DRAMTMG4_T_CCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG4_T_CCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_CCD_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_Pos (24U) +#define DDRCTRL_DRAMTMG4_T_RCD_Msk (0x1FU << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum time from activate to read or write command to same bank. */ +#define DDRCTRL_DRAMTMG4_T_RCD_0 (0x1U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_1 (0x2U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_2 (0x4U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_3 (0x8U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DRAMTMG4_T_RCD_4 (0x10U << DDRCTRL_DRAMTMG4_T_RCD_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG5 register ***************/ +#define DDRCTRL_DRAMTMG5_T_CKE_Pos (0U) +#define DDRCTRL_DRAMTMG5_T_CKE_Msk (0x1FU << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DRAMTMG5_T_CKE DDRCTRL_DRAMTMG5_T_CKE_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. */ +#define DDRCTRL_DRAMTMG5_T_CKE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG5_T_CKE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG5_T_CKE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG5_T_CKE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG5_T_CKE_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_Pos (8U) +#define DDRCTRL_DRAMTMG5_T_CKESR_Msk (0x3FU << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DRAMTMG5_T_CKESR DDRCTRL_DRAMTMG5_T_CKESR_Msk /*!< Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. */ +#define DDRCTRL_DRAMTMG5_T_CKESR_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_4 (0x10U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG5_T_CKESR_5 (0x20U << DDRCTRL_DRAMTMG5_T_CKESR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_Pos (16U) +#define DDRCTRL_DRAMTMG5_T_CKSRE_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE DDRCTRL_DRAMTMG5_T_CKSRE_Msk /*!< This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRE_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRE_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_Pos (24U) +#define DDRCTRL_DRAMTMG5_T_CKSRX_Msk (0xFU << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX DDRCTRL_DRAMTMG5_T_CKSRX_Msk /*!< This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_0 (0x1U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_1 (0x2U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_2 (0x4U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG5_T_CKSRX_3 (0x8U << DDRCTRL_DRAMTMG5_T_CKSRX_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG6 register ***************/ +#define DDRCTRL_DRAMTMG6_T_CKCSX_Pos (0U) +#define DDRCTRL_DRAMTMG6_T_CKCSX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG6_T_CKCSX DDRCTRL_DRAMTMG6_T_CKCSX_Msk /*!< This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG6_T_CKCSX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKCSX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Pos (16U) +#define DDRCTRL_DRAMTMG6_T_CKDPDX_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX DDRCTRL_DRAMTMG6_T_CKDPDX_Msk /*!< This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDX_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Pos (24U) +#define DDRCTRL_DRAMTMG6_T_CKDPDE_Msk (0xFU << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE DDRCTRL_DRAMTMG6_T_CKDPDE_Msk /*!< This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_0 (0x1U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_1 (0x2U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_2 (0x4U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DRAMTMG6_T_CKDPDE_3 (0x8U << DDRCTRL_DRAMTMG6_T_CKDPDE_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG7 register ***************/ +#define DDRCTRL_DRAMTMG7_T_CKPDX_Pos (0U) +#define DDRCTRL_DRAMTMG7_T_CKPDX_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x0000000F */ +#define DDRCTRL_DRAMTMG7_T_CKPDX DDRCTRL_DRAMTMG7_T_CKPDX_Msk /*!< This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG7_T_CKPDX_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDX_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_Pos (8U) +#define DDRCTRL_DRAMTMG7_T_CKPDE_Msk (0xFU << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE DDRCTRL_DRAMTMG7_T_CKPDE_Msk /*!< This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_0 (0x1U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_1 (0x2U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_2 (0x4U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG7_T_CKPDE_3 (0x8U << DDRCTRL_DRAMTMG7_T_CKPDE_Pos) /*!< 0x00000800 */ + +/*************** Bit definition for DDRCTRL_DRAMTMG8 register ***************/ +#define DDRCTRL_DRAMTMG8_T_XS_X32_Pos (0U) +#define DDRCTRL_DRAMTMG8_T_XS_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x0000007F */ +#define DDRCTRL_DRAMTMG8_T_XS_X32 DDRCTRL_DRAMTMG8_T_XS_X32_Msk /*!< tXS: Exit Self Refresh to commands not requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG8_T_XS_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos (8U) +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk (0x7FU << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00007F00 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32 DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Msk /*!< tXSDLL: Exit Self Refresh to the commands requiring a locked DLL. */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_0 (0x1U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_1 (0x2U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_2 (0x4U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_3 (0x8U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_4 (0x10U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_5 (0x20U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DRAMTMG8_T_XS_DLL_X32_6 (0x40U << DDRCTRL_DRAMTMG8_T_XS_DLL_X32_Pos) /*!< 0x00004000 */ + +/************** Bit definition for DDRCTRL_DRAMTMG14 register ***************/ +#define DDRCTRL_DRAMTMG14_T_XSR_Pos (0U) +#define DDRCTRL_DRAMTMG14_T_XSR_Msk (0xFFFU << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000FFF */ +#define DDRCTRL_DRAMTMG14_T_XSR DDRCTRL_DRAMTMG14_T_XSR_Msk /*!< tXSR: Exit Self Refresh to any command. */ +#define DDRCTRL_DRAMTMG14_T_XSR_0 (0x1U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG14_T_XSR_1 (0x2U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG14_T_XSR_2 (0x4U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG14_T_XSR_3 (0x8U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG14_T_XSR_4 (0x10U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG14_T_XSR_5 (0x20U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG14_T_XSR_6 (0x40U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG14_T_XSR_7 (0x80U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG14_T_XSR_8 (0x100U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DRAMTMG14_T_XSR_9 (0x200U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DRAMTMG14_T_XSR_10 (0x400U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DRAMTMG14_T_XSR_11 (0x800U << DDRCTRL_DRAMTMG14_T_XSR_Pos) /*!< 0x00000800 */ + +/************** Bit definition for DDRCTRL_DRAMTMG15 register ***************/ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Pos (0U) +#define DDRCTRL_DRAMTMG15_T_STAB_X32_Msk (0xFFU << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32 DDRCTRL_DRAMTMG15_T_STAB_X32_Msk /*!< tSTAB: Stabilization time. */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_0 (0x1U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_1 (0x2U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_2 (0x4U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_3 (0x8U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_4 (0x10U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_5 (0x20U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_6 (0x40U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DRAMTMG15_T_STAB_X32_7 (0x80U << DDRCTRL_DRAMTMG15_T_STAB_X32_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos (31U) +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk (0x1U << DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. */ + +/**************** Bit definition for DDRCTRL_ZQCTL0 register ****************/ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos (0U) +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x000003FF */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Msk /*!< tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_SHORT_NOP_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos (16U) +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk (0x7FFU << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Msk /*!< tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_0 (0x1U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_1 (0x2U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_2 (0x4U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_3 (0x8U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_4 (0x10U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_5 (0x20U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_6 (0x40U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_7 (0x80U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_8 (0x100U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_9 (0x200U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_10 (0x400U << DDRCTRL_ZQCTL0_T_ZQ_LONG_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos (29U) +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk (0x1U << DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Pos) /*!< 0x20000000 */ +#define DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos (30U) +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Pos) /*!< 0x40000000 */ +#define DDRCTRL_ZQCTL0_DIS_SRX_ZQCL DDRCTRL_ZQCTL0_DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos (31U) +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk (0x1U << DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ZQCTL0_DIS_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. */ + +/**************** Bit definition for DDRCTRL_ZQCTL1 register ****************/ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos (0U) +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk (0xFFFFFU << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x000FFFFF */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Msk /*!< Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_10 (0x400U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_11 (0x800U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_12 (0x1000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_13 (0x2000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_14 (0x4000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00004000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_15 (0x8000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00008000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_16 (0x10000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_17 (0x20000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_18 (0x40000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_19 (0x80000U << DDRCTRL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos (20U) +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk (0x3FFU << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x3FF00000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Msk /*!< tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_0 (0x1U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_1 (0x2U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00200000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_2 (0x4U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00400000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_3 (0x8U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x00800000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_4 (0x10U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_5 (0x20U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_6 (0x40U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_7 (0x80U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_8 (0x100U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_9 (0x200U << DDRCTRL_ZQCTL1_T_ZQ_RESET_NOP_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRCTRL_ZQCTL2 register ****************/ +#define DDRCTRL_ZQCTL2_ZQ_RESET_Pos (0U) +#define DDRCTRL_ZQCTL2_ZQ_RESET_Msk (0x1U << DDRCTRL_ZQCTL2_ZQ_RESET_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQCTL2_ZQ_RESET DDRCTRL_ZQCTL2_ZQ_RESET_Msk /*!< Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the DDRCTRL automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes. */ + +/**************** Bit definition for DDRCTRL_ZQSTAT register ****************/ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos (0U) +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk (0x1U << DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ZQSTAT_ZQ_RESET_BUSY DDRCTRL_ZQSTAT_ZQ_RESET_BUSY_Msk /*!< SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. */ + +/*************** Bit definition for DDRCTRL_DFITMG0 register ****************/ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos (0U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x0000003F */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Msk /*!< Write latency */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRLAT_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos (8U) +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk (0x3FU << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Msk /*!< Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_0 (0x1U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_1 (0x2U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_2 (0x4U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_3 (0x8U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_4 (0x10U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_5 (0x20U << DDRCTRL_DFITMG0_DFI_TPHY_WRDATA_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos (16U) +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk (0x7FU << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x007F0000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Msk /*!< Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_5 (0x20U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_6 (0x40U << DDRCTRL_DFITMG0_DFI_T_RDDATA_EN_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos (24U) +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk (0x1FU << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Msk /*!< Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM\qs/LRDIMM\qs extra cycle of latency in terms of DFI clock. */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_0 (0x1U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_1 (0x2U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_2 (0x4U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_3 (0x8U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_4 (0x10U << DDRCTRL_DFITMG0_DFI_T_CTRL_DELAY_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFITMG1 register ****************/ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos (0U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Msk /*!< Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos (8U) +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Msk /*!< Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos (16U) +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk (0x1FU << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Msk /*!< Specifies the number of DFI clock cycles between when the dfi_wrdata_en */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_0 (0x1U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_1 (0x2U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_2 (0x4U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_3 (0x8U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_4 (0x10U << DDRCTRL_DFITMG1_DFI_T_WRDATA_DELAY_Pos) /*!< 0x00100000 */ + +/************** Bit definition for DDRCTRL_DFILPCFG0 register ***************/ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos (0U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_PD DDRCTRL_DFILPCFG0_DFI_LP_EN_PD_Msk /*!< Enables DFI Low Power interface handshaking during Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos (4U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x000000F0 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_PD_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos (8U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR DDRCTRL_DFILPCFG0_DFI_LP_EN_SR_Msk /*!< Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos (12U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x0000F000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Msk /*!< Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00002000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00004000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_SR_Pos) /*!< 0x00008000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos (16U) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface handshaking during Deep Power Down Entry/Exit. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos (20U) +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk (0xFU << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00F00000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Msk /*!< Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_LP_WAKEUP_DPD_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos (24U) +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk (0x1FU << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Msk /*!< Setting in DFI clock cycles for DFI\qs tlp_resp time. */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_0 (0x1U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_1 (0x2U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_2 (0x4U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_3 (0x8U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_DFILPCFG0_DFI_TLP_RESP_4 (0x10U << DDRCTRL_DFILPCFG0_DFI_TLP_RESP_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD0 register ****************/ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos (0U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x000003FF */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Msk /*!< Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRCTRL expects the PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MIN_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos (16U) +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk (0x3FFU << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x03FF0000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Msk /*!< Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_0 (0x1U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_1 (0x2U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_2 (0x4U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_3 (0x8U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_4 (0x10U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_5 (0x20U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_6 (0x40U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_7 (0x80U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x00800000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_8 (0x100U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_9 (0x200U << DDRCTRL_DFIUPD0_DFI_T_CTRLUP_MAX_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos (29U) +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX DDRCTRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos (30U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos) /*!< 0x40000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos (31U) +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk (0x1U << DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD DDRCTRL_DFIUPD0_DIS_AUTO_CTRLUPD_Msk /*!< When \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. */ + +/*************** Bit definition for DDRCTRL_DFIUPD1 register ****************/ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos (0U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x000000FF */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Msk /*!< This is the maximum amount of time between DDRCTRL initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000040 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_Pos) /*!< 0x00000080 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos (16U) +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk (0xFFU << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Msk /*!< This is the minimum amount of time between DDRCTRL initiated DFI update requests (which is executed whenever the DDRCTRL is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the DDRCTRL is idle. Minimum allowed value for this field is 1. */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_0 (0x1U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_1 (0x2U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_2 (0x4U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_3 (0x8U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_4 (0x10U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_5 (0x20U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00200000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_6 (0x40U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00400000 */ +#define DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_7 (0x80U << DDRCTRL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_Pos) /*!< 0x00800000 */ + +/*************** Bit definition for DDRCTRL_DFIUPD2 register ****************/ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos (31U) +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk (0x1U << DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Pos) /*!< 0x80000000 */ +#define DDRCTRL_DFIUPD2_DFI_PHYUPD_EN DDRCTRL_DFIUPD2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */ + +/*************** Bit definition for DDRCTRL_DFIMISC register ****************/ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos (0U) +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN_Msk /*!< PHY initialization complete enable signal. */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos (4U) +#define DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk (0x1U << DDRCTRL_DFIMISC_CTL_IDLE_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DFIMISC_CTL_IDLE_EN DDRCTRL_DFIMISC_CTL_IDLE_EN_Msk /*!< Enables support of ctl_idle signal */ +#define DDRCTRL_DFIMISC_DFI_INIT_START_Pos (5U) +#define DDRCTRL_DFIMISC_DFI_INIT_START_Msk (0x1U << DDRCTRL_DFIMISC_DFI_INIT_START_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DFIMISC_DFI_INIT_START DDRCTRL_DFIMISC_DFI_INIT_START_Msk /*!< PHY init start request signal.When asserted it triggers the PHY init start request */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos (8U) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk (0x1FU << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY DDRCTRL_DFIMISC_DFI_FREQUENCY_Msk /*!< Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_0 (0x1U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_1 (0x2U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_2 (0x4U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_3 (0x8U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DFIMISC_DFI_FREQUENCY_4 (0x10U << DDRCTRL_DFIMISC_DFI_FREQUENCY_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_DFISTAT register ****************/ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos (0U) +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk (0x1U << DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE DDRCTRL_DFISTAT_DFI_INIT_COMPLETE_Msk /*!< The status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Pos (1U) +#define DDRCTRL_DFISTAT_DFI_LP_ACK_Msk (0x1U << DDRCTRL_DFISTAT_DFI_LP_ACK_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DFISTAT_DFI_LP_ACK DDRCTRL_DFISTAT_DFI_LP_ACK_Msk /*!< Stores the value of the dfi_lp_ack input to the controller. */ + +/************** Bit definition for DDRCTRL_DFIPHYMSTR register **************/ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos (0U) +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk (0x1U << DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN DDRCTRL_DFIPHYMSTR_DFI_PHYMSTR_EN_Msk /*!< Enables the PHY Master Interface: */ + +/*************** Bit definition for DDRCTRL_ADDRMAP1 register ***************/ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos (0U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x0000003F */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Msk /*!< Selects the HIF address bits used as bank address bit 0. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B0_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos (8U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00003F00 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Msk /*!< Selects the HIF address bits used as bank address bit 1. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B1_Pos) /*!< 0x00002000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos (16U) +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk (0x3FU << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x003F0000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2 DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Msk /*!< Selects the HIF address bit used as bank address bit 2. */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_0 (0x1U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_1 (0x2U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_2 (0x4U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_3 (0x8U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_4 (0x10U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_5 (0x20U << DDRCTRL_ADDRMAP1_ADDRMAP_BANK_B2_Pos) /*!< 0x00200000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP2 register ***************/ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos (0U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 2. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos (8U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 3. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos (16U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 4. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos (24U) +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk (0xFU << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 5. */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_0 (0x1U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_1 (0x2U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_2 (0x4U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_3 (0x8U << DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP3 register ***************/ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos (0U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk (0xFU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 6. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos (8U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 7. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Pos) /*!< 0x00001000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos (16U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 8. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos (24U) +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk (0x1FU << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x1F000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 9. */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_0 (0x1U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_1 (0x2U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_2 (0x4U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_3 (0x8U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_4 (0x10U << DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP4 register ***************/ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos (0U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x0000001F */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos (8U) +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk (0x1FU << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_0 (0x1U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_1 (0x2U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_2 (0x4U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_3 (0x8U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_4 (0x10U << DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Pos) /*!< 0x00001000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP5 register ***************/ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos (0U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Msk /*!< Selects the HIF address bits used as row address bit 0. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B0_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos (8U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Msk /*!< Selects the HIF address bits used as row address bit 1. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B1_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos (16U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Msk /*!< Selects the HIF address bits used as row address bits 2 to 10. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B2_10_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos (24U) +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk (0xFU << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11 DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Msk /*!< Selects the HIF address bit used as row address bit 11. */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_0 (0x1U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_1 (0x2U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_2 (0x4U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_3 (0x8U << DDRCTRL_ADDRMAP5_ADDRMAP_ROW_B11_Pos) /*!< 0x08000000 */ + +/*************** Bit definition for DDRCTRL_ADDRMAP6 register ***************/ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos (0U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Msk /*!< Selects the HIF address bit used as row address bit 12. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B12_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos (8U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Msk /*!< Selects the HIF address bit used as row address bit 13. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B13_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos (16U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Msk /*!< Selects the HIF address bit used as row address bit 14. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B14_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos (24U) +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk (0xFU << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15 DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Msk /*!< Selects the HIF address bit used as row address bit 15. */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_0 (0x1U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_1 (0x2U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_2 (0x4U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_3 (0x8U << DDRCTRL_ADDRMAP6_ADDRMAP_ROW_B15_Pos) /*!< 0x08000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos (31U) +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk (0x1U << DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Pos) /*!< 0x80000000 */ +#define DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB DDRCTRL_ADDRMAP6_LPDDR3_6GB_12GB_Msk /*!< Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. */ + +/*************** Bit definition for DDRCTRL_ADDRMAP9 register ***************/ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos (0U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Msk /*!< Selects the HIF address bits used as row address bit 2. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B2_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos (8U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Msk /*!< Selects the HIF address bits used as row address bit 3. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B3_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos (16U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Msk /*!< Selects the HIF address bits used as row address bit 4. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B4_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos (24U) +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk (0xFU << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5 DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Msk /*!< Selects the HIF address bits used as row address bit 5. */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_0 (0x1U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_1 (0x2U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_2 (0x4U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_3 (0x8U << DDRCTRL_ADDRMAP9_ADDRMAP_ROW_B5_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP10 register ***************/ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos (0U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Msk /*!< Selects the HIF address bits used as row address bit 6. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B6_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos (8U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Msk /*!< Selects the HIF address bits used as row address bit 7. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B7_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos (16U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x000F0000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Msk /*!< Selects the HIF address bits used as row address bit 8. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B8_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos (24U) +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk (0xFU << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9 DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Msk /*!< Selects the HIF address bits used as row address bit 9. */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_0 (0x1U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_1 (0x2U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_2 (0x4U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_3 (0x8U << DDRCTRL_ADDRMAP10_ADDRMAP_ROW_B9_Pos) /*!< 0x08000000 */ + +/************** Bit definition for DDRCTRL_ADDRMAP11 register ***************/ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos (0U) +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk (0xFU << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x0000000F */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10 DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Msk /*!< Selects the HIF address bits used as row address bit 10. */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_0 (0x1U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_1 (0x2U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000002 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_2 (0x4U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_3 (0x8U << DDRCTRL_ADDRMAP11_ADDRMAP_ROW_B10_Pos) /*!< 0x00000008 */ + +/**************** Bit definition for DDRCTRL_ODTCFG register ****************/ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos (2U) +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x0000007C */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY DDRCTRL_ODTCFG_RD_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_ODTCFG_RD_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_RD_ODT_DELAY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos (8U) +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD DDRCTRL_ODTCFG_RD_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000100 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000200 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000400 */ +#define DDRCTRL_ODTCFG_RD_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_RD_ODT_HOLD_Pos) /*!< 0x00000800 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos (16U) +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk (0x1FU << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY DDRCTRL_ODTCFG_WR_ODT_DELAY_Msk /*!< The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRCTRL. */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00010000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00020000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00040000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00080000 */ +#define DDRCTRL_ODTCFG_WR_ODT_DELAY_4 (0x10U << DDRCTRL_ODTCFG_WR_ODT_DELAY_Pos) /*!< 0x00100000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos (24U) +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk (0xFU << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x0F000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD DDRCTRL_ODTCFG_WR_ODT_HOLD_Msk /*!< DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_0 (0x1U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x01000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_1 (0x2U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x02000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_2 (0x4U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x04000000 */ +#define DDRCTRL_ODTCFG_WR_ODT_HOLD_3 (0x8U << DDRCTRL_ODTCFG_WR_ODT_HOLD_Pos) /*!< 0x08000000 */ + +/**************** Bit definition for DDRCTRL_ODTMAP register ****************/ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos (0U) +#define DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_WR_ODT_Pos) /*!< 0x00000001 */ +#define DDRCTRL_ODTMAP_RANK0_WR_ODT DDRCTRL_ODTMAP_RANK0_WR_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a write to rank 0. */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos (4U) +#define DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk (0x1U << DDRCTRL_ODTMAP_RANK0_RD_ODT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_ODTMAP_RANK0_RD_ODT DDRCTRL_ODTMAP_RANK0_RD_ODT_Msk /*!< Indicates which remote ODTs must be turned on during a read from rank 0. */ + +/**************** Bit definition for DDRCTRL_SCHED register *****************/ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos (0U) +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk (0x1U << DDRCTRL_SCHED_FORCE_LOW_PRI_N_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED_FORCE_LOW_PRI_N DDRCTRL_SCHED_FORCE_LOW_PRI_N_Msk /*!< Active low signal. When asserted (\q0\q), all incoming transactions are forced to low priority. This implies that all high priority read (HPR) and variable priority read commands (VPR) are treated as low priority read (LPR) commands. On the write side, all variable priority write (VPW) commands are treated as normal priority write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off bypass path for read commands. */ +#define DDRCTRL_SCHED_PREFER_WRITE_Pos (1U) +#define DDRCTRL_SCHED_PREFER_WRITE_Msk (0x1U << DDRCTRL_SCHED_PREFER_WRITE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED_PREFER_WRITE DDRCTRL_SCHED_PREFER_WRITE_Msk /*!< If set then the bank selector prefers writes over reads. */ +#define DDRCTRL_SCHED_PAGECLOSE_Pos (2U) +#define DDRCTRL_SCHED_PAGECLOSE_Msk (0x1U << DDRCTRL_SCHED_PAGECLOSE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED_PAGECLOSE DDRCTRL_SCHED_PAGECLOSE_Msk /*!< If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between write and read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos (8U) +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk (0xFU << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES DDRCTRL_SCHED_LPR_NUM_ENTRIES_Msk /*!< Number of entries in the low priority transaction store is this value + 1. */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_0 (0x1U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000100 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_1 (0x2U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000200 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_2 (0x4U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000400 */ +#define DDRCTRL_SCHED_LPR_NUM_ENTRIES_3 (0x8U << DDRCTRL_SCHED_LPR_NUM_ENTRIES_Pos) /*!< 0x00000800 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos (16U) +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk (0xFFU << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00FF0000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Msk /*!< UNUSED */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_0 (0x1U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00010000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_1 (0x2U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00020000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_2 (0x4U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00040000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_3 (0x8U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00080000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_4 (0x10U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00100000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_5 (0x20U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00200000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_6 (0x40U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00400000 */ +#define DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_7 (0x80U << DDRCTRL_SCHED_GO2CRITICAL_HYSTERESIS_Pos) /*!< 0x00800000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos (24U) +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk (0x7FU << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x7F000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP DDRCTRL_SCHED_RDWR_IDLE_GAP_Msk /*!< When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_0 (0x1U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x01000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_1 (0x2U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x02000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_2 (0x4U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x04000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_3 (0x8U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x08000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_4 (0x10U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x10000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_5 (0x20U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x20000000 */ +#define DDRCTRL_SCHED_RDWR_IDLE_GAP_6 (0x40U << DDRCTRL_SCHED_RDWR_IDLE_GAP_Pos) /*!< 0x40000000 */ + +/**************** Bit definition for DDRCTRL_SCHED1 register ****************/ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos (0U) +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk (0xFFU << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x000000FF */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER DDRCTRL_SCHED1_PAGECLOSE_TIMER_Msk /*!< This field works in conjunction with SCHED.pageclose. */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_0 (0x1U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_1 (0x2U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000002 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_2 (0x4U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000004 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_3 (0x8U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000008 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_4 (0x10U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000010 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_5 (0x20U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000020 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_6 (0x40U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000040 */ +#define DDRCTRL_SCHED1_PAGECLOSE_TIMER_7 (0x80U << DDRCTRL_SCHED1_PAGECLOSE_TIMER_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRCTRL_PERFHPR1 register ***************/ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFHPR1_HPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFHPR1_HPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the HPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFHPR1_HPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFLPR1 register ***************/ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Msk /*!< Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_0 (0x1U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_1 (0x2U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_2 (0x4U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_3 (0x8U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_4 (0x10U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_5 (0x20U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_6 (0x40U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_7 (0x80U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_8 (0x100U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_9 (0x200U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_10 (0x400U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_11 (0x800U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFLPR1_LPR_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFLPR1_LPR_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the LPR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFLPR1_LPR_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRCTRL_PERFWR1 register ****************/ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Pos (0U) +#define DDRCTRL_PERFWR1_W_MAX_STARVE_Msk (0xFFFFU << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x0000FFFF */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE DDRCTRL_PERFWR1_W_MAX_STARVE_Msk /*!< Number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality; during normal operation, this function must not be disabled as it causes excessive latencies. */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_0 (0x1U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_1 (0x2U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_2 (0x4U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_3 (0x8U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_4 (0x10U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_5 (0x20U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_6 (0x40U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_7 (0x80U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_8 (0x100U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_9 (0x200U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_10 (0x400U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_11 (0x800U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_12 (0x1000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_13 (0x2000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_14 (0x4000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PERFWR1_W_MAX_STARVE_15 (0x8000U << DDRCTRL_PERFWR1_W_MAX_STARVE_Pos) /*!< 0x00008000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos (24U) +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk (0xFFU << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0xFF000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Msk /*!< Number of transactions that are serviced once the WR queue goes critical is the smaller of: */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_0 (0x1U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_1 (0x2U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_2 (0x4U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x04000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_3 (0x8U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x08000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_4 (0x10U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x10000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_5 (0x20U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x20000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_6 (0x40U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x40000000 */ +#define DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_7 (0x80U << DDRCTRL_PERFWR1_W_XACT_RUN_LENGTH_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRCTRL_DBG0 register *****************/ +#define DDRCTRL_DBG0_DIS_WC_Pos (0U) +#define DDRCTRL_DBG0_DIS_WC_Msk (0x1U << DDRCTRL_DBG0_DIS_WC_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG0_DIS_WC DDRCTRL_DBG0_DIS_WC_Msk /*!< When 1, disable write combine. */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos (4U) +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk (0x1U << DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT DDRCTRL_DBG0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). */ + +/***************** Bit definition for DDRCTRL_DBG1 register *****************/ +#define DDRCTRL_DBG1_DIS_DQ_Pos (0U) +#define DDRCTRL_DBG1_DIS_DQ_Msk (0x1U << DDRCTRL_DBG1_DIS_DQ_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBG1_DIS_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. */ +#define DDRCTRL_DBG1_DIS_HIF_Pos (1U) +#define DDRCTRL_DBG1_DIS_HIF_Msk (0x1U << DDRCTRL_DBG1_DIS_HIF_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBG1_DIS_HIF DDRCTRL_DBG1_DIS_HIF_Msk /*!< When 1, DDRCTRL asserts the HIF command signal hif_cmd_stall. DDRCTRL ignores the hif_cmd_valid and all other associated request signals. */ + +/**************** Bit definition for DDRCTRL_DBGCAM register ****************/ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos (0U) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x0000001F */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Msk /*!< High priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000002 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000004 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000008 */ +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos (8U) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001F00 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Msk /*!< Low priority read queue depth */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000100 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000200 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000400 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00000800 */ +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH_Pos) /*!< 0x00001000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos (16U) +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk (0x1FU << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x001F0000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Msk /*!< Write queue depth */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_0 (0x1U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00010000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_1 (0x2U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00020000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_2 (0x4U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00040000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_3 (0x8U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00080000 */ +#define DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_4 (0x10U << DDRCTRL_DBGCAM_DBG_W_Q_DEPTH_Pos) /*!< 0x00100000 */ +#define DDRCTRL_DBGCAM_DBG_STALL_Pos (24U) +#define DDRCTRL_DBGCAM_DBG_STALL_Msk (0x1U << DDRCTRL_DBGCAM_DBG_STALL_Pos) /*!< 0x01000000 */ +#define DDRCTRL_DBGCAM_DBG_STALL DDRCTRL_DBGCAM_DBG_STALL_Msk /*!< Stall */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos (25U) +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Pos) /*!< 0x02000000 */ +#define DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY DDRCTRL_DBGCAM_DBG_RD_Q_EMPTY_Msk /*!< When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos (26U) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Pos) /*!< 0x04000000 */ +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY_Msk /*!< When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos (28U) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Pos) /*!< 0x10000000 */ +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos (29U) +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk (0x1U << DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Pos) /*!< 0x20000000 */ +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY_Msk /*!< This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. */ + +/**************** Bit definition for DDRCTRL_DBGCMD register ****************/ +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Pos (0U) +#define DDRCTRL_DBGCMD_RANK0_REFRESH_Msk (0x1U << DDRCTRL_DBGCMD_RANK0_REFRESH_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGCMD_RANK0_REFRESH DDRCTRL_DBGCMD_RANK0_REFRESH_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRCTRL. */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos (4U) +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk (0x1U << DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGCMD_ZQ_CALIB_SHORT DDRCTRL_DBGCMD_ZQ_CALIB_SHORT_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down operating modes or maximum power saving mode. */ +#define DDRCTRL_DBGCMD_CTRLUPD_Pos (5U) +#define DDRCTRL_DBGCMD_CTRLUPD_Msk (0x1U << DDRCTRL_DBGCMD_CTRLUPD_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGCMD_CTRLUPD DDRCTRL_DBGCMD_CTRLUPD_Msk /*!< Setting this register bit to 1 indicates to the DDRCTRL to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the DDRCTRL, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. */ + +/*************** Bit definition for DDRCTRL_DBGSTAT register ****************/ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos (0U) +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY_Msk /*!< SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRCTRL. It is recommended not to perform rank0_refresh operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos (4U) +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY DDRCTRL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_Msk /*!< SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRCTRL. It is recommended not to perform ZQCS operations when this signal is high. */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos (5U) +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk (0x1U << DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_DBGSTAT_CTRLUPD_BUSY DDRCTRL_DBGSTAT_CTRLUPD_BUSY_Msk /*!< SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRCTRL accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRCTRL. It is recommended not to perform ctrlupd operations when this signal is high. */ + +/**************** Bit definition for DDRCTRL_SWCTL register *****************/ +#define DDRCTRL_SWCTL_SW_DONE_Pos (0U) +#define DDRCTRL_SWCTL_SW_DONE_Msk (0x1U << DDRCTRL_SWCTL_SW_DONE_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWCTL_SW_DONE DDRCTRL_SWCTL_SW_DONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. */ + +/**************** Bit definition for DDRCTRL_SWSTAT register ****************/ +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Pos (0U) +#define DDRCTRL_SWSTAT_SW_DONE_ACK_Msk (0x1U << DDRCTRL_SWSTAT_SW_DONE_ACK_Pos) /*!< 0x00000001 */ +#define DDRCTRL_SWSTAT_SW_DONE_ACK DDRCTRL_SWSTAT_SW_DONE_ACK_Msk /*!< Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. */ + +/************** Bit definition for DDRCTRL_POISONCFG register ***************/ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos (0U) +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN DDRCTRL_POISONCFG_WR_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos (4U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Pos) /*!< 0x00000010 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_EN DDRCTRL_POISONCFG_WR_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for write transaction poisoning */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos (8U) +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Pos) /*!< 0x00000100 */ +#define DDRCTRL_POISONCFG_WR_POISON_INTR_CLR DDRCTRL_POISONCFG_WR_POISON_INTR_CLR_Msk /*!< Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos (16U) +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN DDRCTRL_POISONCFG_RD_POISON_SLVERR_EN_Msk /*!< If set to 1, enables SLVERR response for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos (20U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Pos) /*!< 0x00100000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_EN DDRCTRL_POISONCFG_RD_POISON_INTR_EN_Msk /*!< If set to 1, enables interrupts for read transaction poisoning */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos (24U) +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk (0x1U << DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_POISONCFG_RD_POISON_INTR_CLR DDRCTRL_POISONCFG_RD_POISON_INTR_CLR_Msk /*!< Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. */ + +/************** Bit definition for DDRCTRL_POISONSTAT register **************/ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos (0U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_0 DDRCTRL_POISONSTAT_WR_POISON_INTR_0_Msk /*!< Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos (1U) +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_POISONSTAT_WR_POISON_INTR_1 DDRCTRL_POISONSTAT_WR_POISON_INTR_1_Msk /*!< Write transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos (16U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_0 DDRCTRL_POISONSTAT_RD_POISON_INTR_0_Msk /*!< Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos (17U) +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk (0x1U << DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_POISONSTAT_RD_POISON_INTR_1 DDRCTRL_POISONSTAT_RD_POISON_INTR_1_Msk /*!< Read transaction poisoning error interrupt for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port\qs read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. */ + +/**************** Bit definition for DDRCTRL_PSTAT register *****************/ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos (0U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_0_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 DDRCTRL_PSTAT_RD_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding reads for AXI port 0. */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos (1U) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_RD_PORT_BUSY_1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 DDRCTRL_PSTAT_RD_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding reads for AXI port 1. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos (16U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 DDRCTRL_PSTAT_WR_PORT_BUSY_0_Msk /*!< Indicates if there are outstanding writes for AXI port 0. */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos (17U) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk (0x1U << DDRCTRL_PSTAT_WR_PORT_BUSY_1_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 DDRCTRL_PSTAT_WR_PORT_BUSY_1_Msk /*!< Indicates if there are outstanding writes for AXI port 1. */ + +/**************** Bit definition for DDRCTRL_PCCFG register *****************/ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos (0U) +#define DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk (0x1U << DDRCTRL_PCCFG_GO2CRITICAL_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCCFG_GO2CRITICAL_EN DDRCTRL_PCCFG_GO2CRITICAL_EN_Msk /*!< If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b\q0. */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos (4U) +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk (0x1U << DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCCFG_PAGEMATCH_LIMIT DDRCTRL_PCCFG_PAGEMATCH_LIMIT_Msk /*!< Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. */ +#define DDRCTRL_PCCFG_BL_EXP_MODE_Pos (8U) +#define DDRCTRL_PCCFG_BL_EXP_MODE_Msk (0x1U << DDRCTRL_PCCFG_BL_EXP_MODE_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCCFG_BL_EXP_MODE DDRCTRL_PCCFG_BL_EXP_MODE_Msk /*!< Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI uses half of the memory burst length as a unit. */ + +/*************** Bit definition for DDRCTRL_PCFGR_0 register ****************/ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_0_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_AGING_EN DDRCTRL_PCFGR_0_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN DDRCTRL_PCFGR_0_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_0_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_0_RDWR_ORDERED_EN DDRCTRL_PCFGR_0_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_0 register ****************/ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_0_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_AGING_EN DDRCTRL_PCFGW_0_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN DDRCTRL_PCFGW_0_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_0_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_0 register ****************/ +#define DDRCTRL_PCTRL_0_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_0_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_0_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_0_PORT_EN DDRCTRL_PCTRL_0_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_0 register **************/ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_0_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_0 register **************/ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_0 register **************/ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_0_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_0 register **************/ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_0_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/*************** Bit definition for DDRCTRL_PCFGR_1 register ****************/ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Msk /*!< Determines the initial load value of read aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGR_1_RD_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_AGING_EN DDRCTRL_PCFGR_1_RD_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the read channel of the port. */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN DDRCTRL_PCFGR_1_RD_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN DDRCTRL_PCFGR_1_RD_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos (16U) +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk (0x1U << DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGR_1_RDWR_ORDERED_EN DDRCTRL_PCFGR_1_RDWR_ORDERED_EN_Msk /*!< Enables ordered read/writes. If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. Note that this register has an effect only if necessary logic is instantiated via the UMCTL2_RDWR_ORDERED_n parameter. */ + +/*************** Bit definition for DDRCTRL_PCFGW_1 register ****************/ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos (0U) +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk (0x3FFU << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x000003FF */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Msk /*!< Determines the initial load value of write aging counters. These counters are parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port\qs priority increases as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel has the highest priority level. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_0 (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_1 (0x2U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_2 (0x4U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_3 (0x8U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_4 (0x10U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_5 (0x20U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_6 (0x40U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_7 (0x80U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_8 (0x100U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_9 (0x200U << DDRCTRL_PCFGW_1_WR_PORT_PRIORITY_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos (12U) +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Pos) /*!< 0x00001000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_AGING_EN DDRCTRL_PCFGW_1_WR_PORT_AGING_EN_Msk /*!< If set to 1, enables aging function for the write channel of the port. */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos (13U) +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Pos) /*!< 0x00002000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN DDRCTRL_PCFGW_1_WR_PORT_URGENT_EN_Msk /*!< If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos (14U) +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk (0x1U << DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Pos) /*!< 0x00004000 */ +#define DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN DDRCTRL_PCFGW_1_WR_PORT_PAGEMATCH_EN_Msk /*!< If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register. */ + +/*************** Bit definition for DDRCTRL_PCTRL_1 register ****************/ +#define DDRCTRL_PCTRL_1_PORT_EN_Pos (0U) +#define DDRCTRL_PCTRL_1_PORT_EN_Msk (0x1U << DDRCTRL_PCTRL_1_PORT_EN_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCTRL_1_PORT_EN DDRCTRL_PCTRL_1_PORT_EN_Msk /*!< Enables AXI port n. */ + +/************** Bit definition for DDRCTRL_PCFGQOS0_1 register **************/ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Msk /*!< Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2 DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region2. */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGQOS0_1_RQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************** Bit definition for DDRCTRL_PCFGQOS1_1 register **************/ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos (0U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Msk /*!< Specifies the timeout value for transactions mapped to the blue address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos (16U) +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk (0x7FFU << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Msk /*!< Specifies the timeout value for transactions mapped to the red address queue. */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_0 (0x1U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_1 (0x2U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_2 (0x4U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_3 (0x8U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_4 (0x10U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_5 (0x20U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_6 (0x40U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_7 (0x80U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_8 (0x100U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_9 (0x200U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_10 (0x400U << DDRCTRL_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_Pos) /*!< 0x04000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS0_1 register **************/ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos (0U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x0000000F */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Msk /*!< Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos (8U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk (0xFU << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000F00 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Msk /*!< Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_2 (0x4U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_3 (0x8U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_LEVEL2_Pos) /*!< 0x00000800 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos (16U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00030000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Msk /*!< This bitfield indicates the traffic class of region 0. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION0_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos (20U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00300000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Msk /*!< This bitfield indicates the traffic class of region 1. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION1_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos (24U) +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk (0x3U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x03000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2 DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Msk /*!< This bitfield indicates the traffic class of region 2. */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_0 (0x1U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_1 (0x2U << DDRCTRL_PCFGWQOS0_1_WQOS_MAP_REGION2_Pos) /*!< 0x02000000 */ + +/************* Bit definition for DDRCTRL_PCFGWQOS1_1 register **************/ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos (0U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x000007FF */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Msk /*!< Specifies the timeout value for write transactions in region 0 and 1. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000001 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000002 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000004 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000008 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000010 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000020 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000040 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000080 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000100 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000200 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT1_Pos) /*!< 0x00000400 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos (16U) +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk (0x7FFU << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x07FF0000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2 DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Msk /*!< Specifies the timeout value for write transactions in region 2. */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_0 (0x1U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00010000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_1 (0x2U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00020000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_2 (0x4U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00040000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_3 (0x8U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00080000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_4 (0x10U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00100000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_5 (0x20U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00200000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_6 (0x40U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00400000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_7 (0x80U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x00800000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_8 (0x100U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x01000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_9 (0x200U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x02000000 */ +#define DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_10 (0x400U << DDRCTRL_PCFGWQOS1_1_WQOS_MAP_TIMEOUT2_Pos) /*!< 0x04000000 */ + +/******************************************************************************/ +/* */ +/* DDRPERFM block description (DDRPERFM) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for DDRPERFM_CTL register *****************/ +#define DDRPERFM_CTL_START_Pos (0U) +#define DDRPERFM_CTL_START_Msk (0x1U << DDRPERFM_CTL_START_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CTL_START DDRPERFM_CTL_START_Msk /*!< Start counters which are enabled, the time counter (TCNT) is always enabled. */ +#define DDRPERFM_CTL_STOP_Pos (1U) +#define DDRPERFM_CTL_STOP_Msk (0x1U << DDRPERFM_CTL_STOP_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CTL_STOP DDRPERFM_CTL_STOP_Msk /*!< stop all the counters. */ + +/***************** Bit definition for DDRPERFM_CFG register *****************/ +#define DDRPERFM_CFG_EN_Pos (0U) +#define DDRPERFM_CFG_EN_Msk (0xFU << DDRPERFM_CFG_EN_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CFG_EN DDRPERFM_CFG_EN_Msk /*!< enable counter x (from 0 to 3) */ +#define DDRPERFM_CFG_EN_0 (0x1U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CFG_EN_1 (0x2U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CFG_EN_2 (0x4U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CFG_EN_3 (0x8U << DDRPERFM_CFG_EN_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CFG_SEL_Pos (16U) +#define DDRPERFM_CFG_SEL_Msk (0x3U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00030000 */ +#define DDRPERFM_CFG_SEL DDRPERFM_CFG_SEL_Msk /*!< select set of signals to be monitored (from 0 to 3) (see signal set description in Table 34: DDRPERFM signal sets) and counters to be enabled */ +#define DDRPERFM_CFG_SEL_0 (0x1U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CFG_SEL_1 (0x2U << DDRPERFM_CFG_SEL_Pos) /*!< 0x00020000 */ + +/*************** Bit definition for DDRPERFM_STATUS register ****************/ +#define DDRPERFM_STATUS_COVF_Pos (0U) +#define DDRPERFM_STATUS_COVF_Msk (0xFU << DDRPERFM_STATUS_COVF_Pos) /*!< 0x0000000F */ +#define DDRPERFM_STATUS_COVF DDRPERFM_STATUS_COVF_Msk /*!< Counter x Overflow (with x from 0 to 3) */ +#define DDRPERFM_STATUS_COVF_0 (0x1U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_STATUS_COVF_1 (0x2U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000002 */ +#define DDRPERFM_STATUS_COVF_2 (0x4U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000004 */ +#define DDRPERFM_STATUS_COVF_3 (0x8U << DDRPERFM_STATUS_COVF_Pos) /*!< 0x00000008 */ +#define DDRPERFM_STATUS_BUSY_Pos (16U) +#define DDRPERFM_STATUS_BUSY_Msk (0x1U << DDRPERFM_STATUS_BUSY_Pos) /*!< 0x00010000 */ +#define DDRPERFM_STATUS_BUSY DDRPERFM_STATUS_BUSY_Msk /*!< Busy Status */ +#define DDRPERFM_STATUS_TOVF_Pos (31U) +#define DDRPERFM_STATUS_TOVF_Msk (0x1U << DDRPERFM_STATUS_TOVF_Pos) /*!< 0x80000000 */ +#define DDRPERFM_STATUS_TOVF DDRPERFM_STATUS_TOVF_Msk /*!< total counter overflow */ + +/***************** Bit definition for DDRPERFM_CCR register *****************/ +#define DDRPERFM_CCR_CCLR_Pos (0U) +#define DDRPERFM_CCR_CCLR_Msk (0xFU << DDRPERFM_CCR_CCLR_Pos) /*!< 0x0000000F */ +#define DDRPERFM_CCR_CCLR DDRPERFM_CCR_CCLR_Msk /*!< counter x Clear (with x from 0 to 3) */ +#define DDRPERFM_CCR_CCLR_0 (0x1U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CCR_CCLR_1 (0x2U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CCR_CCLR_2 (0x4U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CCR_CCLR_3 (0x8U << DDRPERFM_CCR_CCLR_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CCR_TCLR_Pos (31U) +#define DDRPERFM_CCR_TCLR_Msk (0x1U << DDRPERFM_CCR_TCLR_Pos) /*!< 0x80000000 */ +#define DDRPERFM_CCR_TCLR DDRPERFM_CCR_TCLR_Msk /*!< time counter clear */ + +/***************** Bit definition for DDRPERFM_IER register *****************/ +#define DDRPERFM_IER_OVFIE_Pos (0U) +#define DDRPERFM_IER_OVFIE_Msk (0x1U << DDRPERFM_IER_OVFIE_Pos) /*!< 0x00000001 */ +#define DDRPERFM_IER_OVFIE DDRPERFM_IER_OVFIE_Msk /*!< overflow interrupt enable */ + +/***************** Bit definition for DDRPERFM_ISR register *****************/ +#define DDRPERFM_ISR_OVFF_Pos (0U) +#define DDRPERFM_ISR_OVFF_Msk (0x1U << DDRPERFM_ISR_OVFF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ISR_OVFF DDRPERFM_ISR_OVFF_Msk /*!< overflow flag */ + +/***************** Bit definition for DDRPERFM_ICR register *****************/ +#define DDRPERFM_ICR_OVF_Pos (0U) +#define DDRPERFM_ICR_OVF_Msk (0x1U << DDRPERFM_ICR_OVF_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ICR_OVF DDRPERFM_ICR_OVF_Msk /*!< overflow flag */ + +/**************** Bit definition for DDRPERFM_TCNT register *****************/ +#define DDRPERFM_TCNT_CNT_Pos (0U) +#define DDRPERFM_TCNT_CNT_Msk (0xFFFFFFFFU << DDRPERFM_TCNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_TCNT_CNT DDRPERFM_TCNT_CNT_Msk /*!< total time, this is number of DDR controller clocks elapsed while DDRPERFM has been running. */ +#define DDRPERFM_TCNT_CNT_0 (0x1U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_TCNT_CNT_1 (0x2U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_TCNT_CNT_2 (0x4U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_TCNT_CNT_3 (0x8U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_TCNT_CNT_4 (0x10U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_TCNT_CNT_5 (0x20U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_TCNT_CNT_6 (0x40U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_TCNT_CNT_7 (0x80U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_TCNT_CNT_8 (0x100U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_TCNT_CNT_9 (0x200U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_TCNT_CNT_10 (0x400U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_TCNT_CNT_11 (0x800U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_TCNT_CNT_12 (0x1000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_TCNT_CNT_13 (0x2000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_TCNT_CNT_14 (0x4000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_TCNT_CNT_15 (0x8000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_TCNT_CNT_16 (0x10000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_TCNT_CNT_17 (0x20000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_TCNT_CNT_18 (0x40000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_TCNT_CNT_19 (0x80000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_TCNT_CNT_20 (0x100000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_TCNT_CNT_21 (0x200000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_TCNT_CNT_22 (0x400000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_TCNT_CNT_23 (0x800000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_TCNT_CNT_24 (0x1000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_TCNT_CNT_25 (0x2000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_TCNT_CNT_26 (0x4000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_TCNT_CNT_27 (0x8000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_TCNT_CNT_28 (0x10000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_TCNT_CNT_29 (0x20000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_TCNT_CNT_30 (0x40000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_TCNT_CNT_31 (0x80000000U << DDRPERFM_TCNT_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT0 register *****************/ +#define DDRPERFM_CNT0_CNT_Pos (0U) +#define DDRPERFM_CNT0_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT0_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT0_CNT DDRPERFM_CNT0_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT0_CNT_0 (0x1U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT0_CNT_1 (0x2U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT0_CNT_2 (0x4U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT0_CNT_3 (0x8U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT0_CNT_4 (0x10U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT0_CNT_5 (0x20U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT0_CNT_6 (0x40U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT0_CNT_7 (0x80U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT0_CNT_8 (0x100U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT0_CNT_9 (0x200U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT0_CNT_10 (0x400U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT0_CNT_11 (0x800U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT0_CNT_12 (0x1000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT0_CNT_13 (0x2000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT0_CNT_14 (0x4000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT0_CNT_15 (0x8000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT0_CNT_16 (0x10000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT0_CNT_17 (0x20000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT0_CNT_18 (0x40000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT0_CNT_19 (0x80000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT0_CNT_20 (0x100000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT0_CNT_21 (0x200000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT0_CNT_22 (0x400000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT0_CNT_23 (0x800000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT0_CNT_24 (0x1000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT0_CNT_25 (0x2000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT0_CNT_26 (0x4000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT0_CNT_27 (0x8000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT0_CNT_28 (0x10000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT0_CNT_29 (0x20000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT0_CNT_30 (0x40000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT0_CNT_31 (0x80000000U << DDRPERFM_CNT0_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT1 register *****************/ +#define DDRPERFM_CNT1_CNT_Pos (0U) +#define DDRPERFM_CNT1_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT1_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT1_CNT DDRPERFM_CNT1_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT1_CNT_0 (0x1U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT1_CNT_1 (0x2U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT1_CNT_2 (0x4U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT1_CNT_3 (0x8U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT1_CNT_4 (0x10U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT1_CNT_5 (0x20U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT1_CNT_6 (0x40U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT1_CNT_7 (0x80U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT1_CNT_8 (0x100U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT1_CNT_9 (0x200U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT1_CNT_10 (0x400U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT1_CNT_11 (0x800U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT1_CNT_12 (0x1000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT1_CNT_13 (0x2000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT1_CNT_14 (0x4000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT1_CNT_15 (0x8000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT1_CNT_16 (0x10000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT1_CNT_17 (0x20000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT1_CNT_18 (0x40000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT1_CNT_19 (0x80000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT1_CNT_20 (0x100000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT1_CNT_21 (0x200000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT1_CNT_22 (0x400000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT1_CNT_23 (0x800000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT1_CNT_24 (0x1000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT1_CNT_25 (0x2000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT1_CNT_26 (0x4000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT1_CNT_27 (0x8000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT1_CNT_28 (0x10000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT1_CNT_29 (0x20000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT1_CNT_30 (0x40000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT1_CNT_31 (0x80000000U << DDRPERFM_CNT1_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT2 register *****************/ +#define DDRPERFM_CNT2_CNT_Pos (0U) +#define DDRPERFM_CNT2_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT2_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT2_CNT DDRPERFM_CNT2_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT2_CNT_0 (0x1U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT2_CNT_1 (0x2U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT2_CNT_2 (0x4U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT2_CNT_3 (0x8U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT2_CNT_4 (0x10U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT2_CNT_5 (0x20U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT2_CNT_6 (0x40U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT2_CNT_7 (0x80U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT2_CNT_8 (0x100U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT2_CNT_9 (0x200U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT2_CNT_10 (0x400U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT2_CNT_11 (0x800U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT2_CNT_12 (0x1000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT2_CNT_13 (0x2000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT2_CNT_14 (0x4000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT2_CNT_15 (0x8000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT2_CNT_16 (0x10000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT2_CNT_17 (0x20000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT2_CNT_18 (0x40000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT2_CNT_19 (0x80000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT2_CNT_20 (0x100000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT2_CNT_21 (0x200000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT2_CNT_22 (0x400000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT2_CNT_23 (0x800000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT2_CNT_24 (0x1000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT2_CNT_25 (0x2000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT2_CNT_26 (0x4000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT2_CNT_27 (0x8000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT2_CNT_28 (0x10000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT2_CNT_29 (0x20000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT2_CNT_30 (0x40000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT2_CNT_31 (0x80000000U << DDRPERFM_CNT2_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_CNT3 register *****************/ +#define DDRPERFM_CNT3_CNT_Pos (0U) +#define DDRPERFM_CNT3_CNT_Msk (0xFFFFFFFFU << DDRPERFM_CNT3_CNT_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_CNT3_CNT DDRPERFM_CNT3_CNT_Msk /*!< event counter value. */ +#define DDRPERFM_CNT3_CNT_0 (0x1U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_CNT3_CNT_1 (0x2U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_CNT3_CNT_2 (0x4U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_CNT3_CNT_3 (0x8U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000008 */ +#define DDRPERFM_CNT3_CNT_4 (0x10U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000010 */ +#define DDRPERFM_CNT3_CNT_5 (0x20U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000020 */ +#define DDRPERFM_CNT3_CNT_6 (0x40U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000040 */ +#define DDRPERFM_CNT3_CNT_7 (0x80U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000080 */ +#define DDRPERFM_CNT3_CNT_8 (0x100U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000100 */ +#define DDRPERFM_CNT3_CNT_9 (0x200U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000200 */ +#define DDRPERFM_CNT3_CNT_10 (0x400U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000400 */ +#define DDRPERFM_CNT3_CNT_11 (0x800U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00000800 */ +#define DDRPERFM_CNT3_CNT_12 (0x1000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00001000 */ +#define DDRPERFM_CNT3_CNT_13 (0x2000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00002000 */ +#define DDRPERFM_CNT3_CNT_14 (0x4000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00004000 */ +#define DDRPERFM_CNT3_CNT_15 (0x8000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00008000 */ +#define DDRPERFM_CNT3_CNT_16 (0x10000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00010000 */ +#define DDRPERFM_CNT3_CNT_17 (0x20000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00020000 */ +#define DDRPERFM_CNT3_CNT_18 (0x40000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00040000 */ +#define DDRPERFM_CNT3_CNT_19 (0x80000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00080000 */ +#define DDRPERFM_CNT3_CNT_20 (0x100000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00100000 */ +#define DDRPERFM_CNT3_CNT_21 (0x200000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00200000 */ +#define DDRPERFM_CNT3_CNT_22 (0x400000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00400000 */ +#define DDRPERFM_CNT3_CNT_23 (0x800000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x00800000 */ +#define DDRPERFM_CNT3_CNT_24 (0x1000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x01000000 */ +#define DDRPERFM_CNT3_CNT_25 (0x2000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x02000000 */ +#define DDRPERFM_CNT3_CNT_26 (0x4000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x04000000 */ +#define DDRPERFM_CNT3_CNT_27 (0x8000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x08000000 */ +#define DDRPERFM_CNT3_CNT_28 (0x10000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x10000000 */ +#define DDRPERFM_CNT3_CNT_29 (0x20000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x20000000 */ +#define DDRPERFM_CNT3_CNT_30 (0x40000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x40000000 */ +#define DDRPERFM_CNT3_CNT_31 (0x80000000U << DDRPERFM_CNT3_CNT_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPERFM_HWCFG register ****************/ +#define DDRPERFM_HWCFG_NCNT_Pos (0U) +#define DDRPERFM_HWCFG_NCNT_Msk (0xFU << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x0000000F */ +#define DDRPERFM_HWCFG_NCNT DDRPERFM_HWCFG_NCNT_Msk /*!< number of counters for this configuration (4) */ +#define DDRPERFM_HWCFG_NCNT_0 (0x1U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000001 */ +#define DDRPERFM_HWCFG_NCNT_1 (0x2U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000002 */ +#define DDRPERFM_HWCFG_NCNT_2 (0x4U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000004 */ +#define DDRPERFM_HWCFG_NCNT_3 (0x8U << DDRPERFM_HWCFG_NCNT_Pos) /*!< 0x00000008 */ + +/***************** Bit definition for DDRPERFM_VER register *****************/ +#define DDRPERFM_VER_MINREV_Pos (0U) +#define DDRPERFM_VER_MINREV_Msk (0xFU << DDRPERFM_VER_MINREV_Pos) /*!< 0x0000000F */ +#define DDRPERFM_VER_MINREV DDRPERFM_VER_MINREV_Msk /*!< Minor revision number. */ +#define DDRPERFM_VER_MINREV_0 (0x1U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000001 */ +#define DDRPERFM_VER_MINREV_1 (0x2U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000002 */ +#define DDRPERFM_VER_MINREV_2 (0x4U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000004 */ +#define DDRPERFM_VER_MINREV_3 (0x8U << DDRPERFM_VER_MINREV_Pos) /*!< 0x00000008 */ +#define DDRPERFM_VER_MAJREV_Pos (4U) +#define DDRPERFM_VER_MAJREV_Msk (0xFU << DDRPERFM_VER_MAJREV_Pos) /*!< 0x000000F0 */ +#define DDRPERFM_VER_MAJREV DDRPERFM_VER_MAJREV_Msk /*!< Major revision number. */ +#define DDRPERFM_VER_MAJREV_0 (0x1U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000010 */ +#define DDRPERFM_VER_MAJREV_1 (0x2U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000020 */ +#define DDRPERFM_VER_MAJREV_2 (0x4U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000040 */ +#define DDRPERFM_VER_MAJREV_3 (0x8U << DDRPERFM_VER_MAJREV_Pos) /*!< 0x00000080 */ + +/***************** Bit definition for DDRPERFM_ID register ******************/ +#define DDRPERFM_ID_ID_Pos (0U) +#define DDRPERFM_ID_ID_Msk (0xFFFFFFFFU << DDRPERFM_ID_ID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_ID_ID DDRPERFM_ID_ID_Msk /*!< DDRPERFM unique identification. */ +#define DDRPERFM_ID_ID_0 (0x1U << DDRPERFM_ID_ID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_ID_ID_1 (0x2U << DDRPERFM_ID_ID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_ID_ID_2 (0x4U << DDRPERFM_ID_ID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_ID_ID_3 (0x8U << DDRPERFM_ID_ID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_ID_ID_4 (0x10U << DDRPERFM_ID_ID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_ID_ID_5 (0x20U << DDRPERFM_ID_ID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_ID_ID_6 (0x40U << DDRPERFM_ID_ID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_ID_ID_7 (0x80U << DDRPERFM_ID_ID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_ID_ID_8 (0x100U << DDRPERFM_ID_ID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_ID_ID_9 (0x200U << DDRPERFM_ID_ID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_ID_ID_10 (0x400U << DDRPERFM_ID_ID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_ID_ID_11 (0x800U << DDRPERFM_ID_ID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_ID_ID_12 (0x1000U << DDRPERFM_ID_ID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_ID_ID_13 (0x2000U << DDRPERFM_ID_ID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_ID_ID_14 (0x4000U << DDRPERFM_ID_ID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_ID_ID_15 (0x8000U << DDRPERFM_ID_ID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_ID_ID_16 (0x10000U << DDRPERFM_ID_ID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_ID_ID_17 (0x20000U << DDRPERFM_ID_ID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_ID_ID_18 (0x40000U << DDRPERFM_ID_ID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_ID_ID_19 (0x80000U << DDRPERFM_ID_ID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_ID_ID_20 (0x100000U << DDRPERFM_ID_ID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_ID_ID_21 (0x200000U << DDRPERFM_ID_ID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_ID_ID_22 (0x400000U << DDRPERFM_ID_ID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_ID_ID_23 (0x800000U << DDRPERFM_ID_ID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_ID_ID_24 (0x1000000U << DDRPERFM_ID_ID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_ID_ID_25 (0x2000000U << DDRPERFM_ID_ID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_ID_ID_26 (0x4000000U << DDRPERFM_ID_ID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_ID_ID_27 (0x8000000U << DDRPERFM_ID_ID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_ID_ID_28 (0x10000000U << DDRPERFM_ID_ID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_ID_ID_29 (0x20000000U << DDRPERFM_ID_ID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_ID_ID_30 (0x40000000U << DDRPERFM_ID_ID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_ID_ID_31 (0x80000000U << DDRPERFM_ID_ID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPERFM_SID register *****************/ +#define DDRPERFM_SID_SID_Pos (0U) +#define DDRPERFM_SID_SID_Msk (0xFFFFFFFFU << DDRPERFM_SID_SID_Pos) /*!< 0xFFFFFFFF */ +#define DDRPERFM_SID_SID DDRPERFM_SID_SID_Msk /*!< magic ID for automatic IP discovery. */ +#define DDRPERFM_SID_SID_0 (0x1U << DDRPERFM_SID_SID_Pos) /*!< 0x00000001 */ +#define DDRPERFM_SID_SID_1 (0x2U << DDRPERFM_SID_SID_Pos) /*!< 0x00000002 */ +#define DDRPERFM_SID_SID_2 (0x4U << DDRPERFM_SID_SID_Pos) /*!< 0x00000004 */ +#define DDRPERFM_SID_SID_3 (0x8U << DDRPERFM_SID_SID_Pos) /*!< 0x00000008 */ +#define DDRPERFM_SID_SID_4 (0x10U << DDRPERFM_SID_SID_Pos) /*!< 0x00000010 */ +#define DDRPERFM_SID_SID_5 (0x20U << DDRPERFM_SID_SID_Pos) /*!< 0x00000020 */ +#define DDRPERFM_SID_SID_6 (0x40U << DDRPERFM_SID_SID_Pos) /*!< 0x00000040 */ +#define DDRPERFM_SID_SID_7 (0x80U << DDRPERFM_SID_SID_Pos) /*!< 0x00000080 */ +#define DDRPERFM_SID_SID_8 (0x100U << DDRPERFM_SID_SID_Pos) /*!< 0x00000100 */ +#define DDRPERFM_SID_SID_9 (0x200U << DDRPERFM_SID_SID_Pos) /*!< 0x00000200 */ +#define DDRPERFM_SID_SID_10 (0x400U << DDRPERFM_SID_SID_Pos) /*!< 0x00000400 */ +#define DDRPERFM_SID_SID_11 (0x800U << DDRPERFM_SID_SID_Pos) /*!< 0x00000800 */ +#define DDRPERFM_SID_SID_12 (0x1000U << DDRPERFM_SID_SID_Pos) /*!< 0x00001000 */ +#define DDRPERFM_SID_SID_13 (0x2000U << DDRPERFM_SID_SID_Pos) /*!< 0x00002000 */ +#define DDRPERFM_SID_SID_14 (0x4000U << DDRPERFM_SID_SID_Pos) /*!< 0x00004000 */ +#define DDRPERFM_SID_SID_15 (0x8000U << DDRPERFM_SID_SID_Pos) /*!< 0x00008000 */ +#define DDRPERFM_SID_SID_16 (0x10000U << DDRPERFM_SID_SID_Pos) /*!< 0x00010000 */ +#define DDRPERFM_SID_SID_17 (0x20000U << DDRPERFM_SID_SID_Pos) /*!< 0x00020000 */ +#define DDRPERFM_SID_SID_18 (0x40000U << DDRPERFM_SID_SID_Pos) /*!< 0x00040000 */ +#define DDRPERFM_SID_SID_19 (0x80000U << DDRPERFM_SID_SID_Pos) /*!< 0x00080000 */ +#define DDRPERFM_SID_SID_20 (0x100000U << DDRPERFM_SID_SID_Pos) /*!< 0x00100000 */ +#define DDRPERFM_SID_SID_21 (0x200000U << DDRPERFM_SID_SID_Pos) /*!< 0x00200000 */ +#define DDRPERFM_SID_SID_22 (0x400000U << DDRPERFM_SID_SID_Pos) /*!< 0x00400000 */ +#define DDRPERFM_SID_SID_23 (0x800000U << DDRPERFM_SID_SID_Pos) /*!< 0x00800000 */ +#define DDRPERFM_SID_SID_24 (0x1000000U << DDRPERFM_SID_SID_Pos) /*!< 0x01000000 */ +#define DDRPERFM_SID_SID_25 (0x2000000U << DDRPERFM_SID_SID_Pos) /*!< 0x02000000 */ +#define DDRPERFM_SID_SID_26 (0x4000000U << DDRPERFM_SID_SID_Pos) /*!< 0x04000000 */ +#define DDRPERFM_SID_SID_27 (0x8000000U << DDRPERFM_SID_SID_Pos) /*!< 0x08000000 */ +#define DDRPERFM_SID_SID_28 (0x10000000U << DDRPERFM_SID_SID_Pos) /*!< 0x10000000 */ +#define DDRPERFM_SID_SID_29 (0x20000000U << DDRPERFM_SID_SID_Pos) /*!< 0x20000000 */ +#define DDRPERFM_SID_SID_30 (0x40000000U << DDRPERFM_SID_SID_Pos) /*!< 0x40000000 */ +#define DDRPERFM_SID_SID_31 (0x80000000U << DDRPERFM_SID_SID_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* DDRPHYC block description (DDRPHYC) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DDRPHYC_RIDR register *****************/ +#define DDRPHYC_RIDR_PUBMNR_Pos (0U) +#define DDRPHYC_RIDR_PUBMNR_Msk (0xFU << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x0000000F */ +#define DDRPHYC_RIDR_PUBMNR DDRPHYC_RIDR_PUBMNR_Msk /*!< PUB minor rev */ +#define DDRPHYC_RIDR_PUBMNR_0 (0x1U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_RIDR_PUBMNR_1 (0x2U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_RIDR_PUBMNR_2 (0x4U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_RIDR_PUBMNR_3 (0x8U << DDRPHYC_RIDR_PUBMNR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_RIDR_PUBMDR_Pos (4U) +#define DDRPHYC_RIDR_PUBMDR_Msk (0xFU << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_RIDR_PUBMDR DDRPHYC_RIDR_PUBMDR_Msk /*!< PUB moderate rev */ +#define DDRPHYC_RIDR_PUBMDR_0 (0x1U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_RIDR_PUBMDR_1 (0x2U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_RIDR_PUBMDR_2 (0x4U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_RIDR_PUBMDR_3 (0x8U << DDRPHYC_RIDR_PUBMDR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_RIDR_PUBMJR_Pos (8U) +#define DDRPHYC_RIDR_PUBMJR_Msk (0xFU << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_RIDR_PUBMJR DDRPHYC_RIDR_PUBMJR_Msk /*!< PUB maj rev */ +#define DDRPHYC_RIDR_PUBMJR_0 (0x1U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_RIDR_PUBMJR_1 (0x2U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_RIDR_PUBMJR_2 (0x4U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_RIDR_PUBMJR_3 (0x8U << DDRPHYC_RIDR_PUBMJR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_RIDR_PHYMNR_Pos (12U) +#define DDRPHYC_RIDR_PHYMNR_Msk (0xFU << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_RIDR_PHYMNR DDRPHYC_RIDR_PHYMNR_Msk /*!< PHY minor rev */ +#define DDRPHYC_RIDR_PHYMNR_0 (0x1U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_RIDR_PHYMNR_1 (0x2U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_RIDR_PHYMNR_2 (0x4U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00004000 */ +#define DDRPHYC_RIDR_PHYMNR_3 (0x8U << DDRPHYC_RIDR_PHYMNR_Pos) /*!< 0x00008000 */ +#define DDRPHYC_RIDR_PHYMDR_Pos (16U) +#define DDRPHYC_RIDR_PHYMDR_Msk (0xFU << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_RIDR_PHYMDR DDRPHYC_RIDR_PHYMDR_Msk /*!< PHY moderate rev */ +#define DDRPHYC_RIDR_PHYMDR_0 (0x1U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_RIDR_PHYMDR_1 (0x2U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00020000 */ +#define DDRPHYC_RIDR_PHYMDR_2 (0x4U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00040000 */ +#define DDRPHYC_RIDR_PHYMDR_3 (0x8U << DDRPHYC_RIDR_PHYMDR_Pos) /*!< 0x00080000 */ +#define DDRPHYC_RIDR_PHYMJR_Pos (20U) +#define DDRPHYC_RIDR_PHYMJR_Msk (0xFU << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_RIDR_PHYMJR DDRPHYC_RIDR_PHYMJR_Msk /*!< PHY maj rev */ +#define DDRPHYC_RIDR_PHYMJR_0 (0x1U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00100000 */ +#define DDRPHYC_RIDR_PHYMJR_1 (0x2U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00200000 */ +#define DDRPHYC_RIDR_PHYMJR_2 (0x4U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_RIDR_PHYMJR_3 (0x8U << DDRPHYC_RIDR_PHYMJR_Pos) /*!< 0x00800000 */ +#define DDRPHYC_RIDR_UDRID_Pos (24U) +#define DDRPHYC_RIDR_UDRID_Msk (0xFFU << DDRPHYC_RIDR_UDRID_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */ +#define DDRPHYC_RIDR_UDRID_0 (0x1U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x01000000 */ +#define DDRPHYC_RIDR_UDRID_1 (0x2U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x02000000 */ +#define DDRPHYC_RIDR_UDRID_2 (0x4U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x04000000 */ +#define DDRPHYC_RIDR_UDRID_3 (0x8U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x08000000 */ +#define DDRPHYC_RIDR_UDRID_4 (0x10U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x10000000 */ +#define DDRPHYC_RIDR_UDRID_5 (0x20U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x20000000 */ +#define DDRPHYC_RIDR_UDRID_6 (0x40U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x40000000 */ +#define DDRPHYC_RIDR_UDRID_7 (0x80U << DDRPHYC_RIDR_UDRID_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_PIR register ******************/ +#define DDRPHYC_PIR_INIT_Pos (0U) +#define DDRPHYC_PIR_INIT_Msk (0x1U << DDRPHYC_PIR_INIT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PIR_INIT DDRPHYC_PIR_INIT_Msk /*!< Initialization trigger */ +#define DDRPHYC_PIR_DLLSRST_Pos (1U) +#define DDRPHYC_PIR_DLLSRST_Msk (0x1U << DDRPHYC_PIR_DLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PIR_DLLSRST DDRPHYC_PIR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PIR_DLLLOCK_Pos (2U) +#define DDRPHYC_PIR_DLLLOCK_Msk (0x1U << DDRPHYC_PIR_DLLLOCK_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PIR_DLLLOCK DDRPHYC_PIR_DLLLOCK_Msk /*!< DLL lock */ +#define DDRPHYC_PIR_ZCAL_Pos (3U) +#define DDRPHYC_PIR_ZCAL_Msk (0x1U << DDRPHYC_PIR_ZCAL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PIR_ZCAL DDRPHYC_PIR_ZCAL_Msk /*!< Impedance calibration (Driver and ODT) */ +#define DDRPHYC_PIR_ITMSRST_Pos (4U) +#define DDRPHYC_PIR_ITMSRST_Msk (0x1U << DDRPHYC_PIR_ITMSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PIR_ITMSRST DDRPHYC_PIR_ITMSRST_Msk /*!< ITM reset */ +#define DDRPHYC_PIR_DRAMRST_Pos (5U) +#define DDRPHYC_PIR_DRAMRST_Msk (0x1U << DDRPHYC_PIR_DRAMRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PIR_DRAMRST DDRPHYC_PIR_DRAMRST_Msk /*!< DRAM reset (DDR3 only) */ +#define DDRPHYC_PIR_DRAMINIT_Pos (6U) +#define DDRPHYC_PIR_DRAMINIT_Msk (0x1U << DDRPHYC_PIR_DRAMINIT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PIR_DRAMINIT DDRPHYC_PIR_DRAMINIT_Msk /*!< DRAM initialization */ +#define DDRPHYC_PIR_QSTRN_Pos (7U) +#define DDRPHYC_PIR_QSTRN_Msk (0x1U << DDRPHYC_PIR_QSTRN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PIR_QSTRN DDRPHYC_PIR_QSTRN_Msk /*!< Read DQS training */ +#define DDRPHYC_PIR_RVTRN_Pos (8U) +#define DDRPHYC_PIR_RVTRN_Msk (0x1U << DDRPHYC_PIR_RVTRN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PIR_RVTRN DDRPHYC_PIR_RVTRN_Msk /*!< Read DQS gate training DQSTRN) and RV training (RVTRN) should normally be run */ +#define DDRPHYC_PIR_ICPC_Pos (16U) +#define DDRPHYC_PIR_ICPC_Msk (0x1U << DDRPHYC_PIR_ICPC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PIR_ICPC DDRPHYC_PIR_ICPC_Msk /*!< Initialization complete pin configuration */ +#define DDRPHYC_PIR_DLLBYP_Pos (17U) +#define DDRPHYC_PIR_DLLBYP_Msk (0x1U << DDRPHYC_PIR_DLLBYP_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PIR_DLLBYP DDRPHYC_PIR_DLLBYP_Msk /*!< DLL bypass */ +#define DDRPHYC_PIR_CTLDINIT_Pos (18U) +#define DDRPHYC_PIR_CTLDINIT_Msk (0x1U << DDRPHYC_PIR_CTLDINIT_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PIR_CTLDINIT DDRPHYC_PIR_CTLDINIT_Msk /*!< Controller DRAM initialization */ +#define DDRPHYC_PIR_CLRSR_Pos (28U) +#define DDRPHYC_PIR_CLRSR_Msk (0x1U << DDRPHYC_PIR_CLRSR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PIR_CLRSR DDRPHYC_PIR_CLRSR_Msk /*!< clear status register */ +#define DDRPHYC_PIR_LOCKBYP_Pos (29U) +#define DDRPHYC_PIR_LOCKBYP_Msk (0x1U << DDRPHYC_PIR_LOCKBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PIR_LOCKBYP DDRPHYC_PIR_LOCKBYP_Msk /*!< DLL lock bypass */ +#define DDRPHYC_PIR_ZCALBYP_Pos (30U) +#define DDRPHYC_PIR_ZCALBYP_Msk (0x1U << DDRPHYC_PIR_ZCALBYP_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PIR_ZCALBYP DDRPHYC_PIR_ZCALBYP_Msk /*!< zcal bypass */ +#define DDRPHYC_PIR_INITBYP_Pos (31U) +#define DDRPHYC_PIR_INITBYP_Msk (0x1U << DDRPHYC_PIR_INITBYP_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PIR_INITBYP DDRPHYC_PIR_INITBYP_Msk /*!< Initialization bypass */ + +/***************** Bit definition for DDRPHYC_PGCR register *****************/ +#define DDRPHYC_PGCR_ITMDMD_Pos (0U) +#define DDRPHYC_PGCR_ITMDMD_Msk (0x1U << DDRPHYC_PGCR_ITMDMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGCR_ITMDMD DDRPHYC_PGCR_ITMDMD_Msk /*!< ITM DDR mode */ +#define DDRPHYC_PGCR_DQSCFG_Pos (1U) +#define DDRPHYC_PGCR_DQSCFG_Msk (0x1U << DDRPHYC_PGCR_DQSCFG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGCR_DQSCFG DDRPHYC_PGCR_DQSCFG_Msk /*!< DQS gating configuration */ +#define DDRPHYC_PGCR_DFTCMP_Pos (2U) +#define DDRPHYC_PGCR_DFTCMP_Msk (0x1U << DDRPHYC_PGCR_DFTCMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGCR_DFTCMP DDRPHYC_PGCR_DFTCMP_Msk /*!< DQS drift compensation */ +#define DDRPHYC_PGCR_DFTLMT_Pos (3U) +#define DDRPHYC_PGCR_DFTLMT_Msk (0x3U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000018 */ +#define DDRPHYC_PGCR_DFTLMT DDRPHYC_PGCR_DFTLMT_Msk /*!< DQS drift limit */ +#define DDRPHYC_PGCR_DFTLMT_0 (0x1U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGCR_DFTLMT_1 (0x2U << DDRPHYC_PGCR_DFTLMT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGCR_DTOSEL_Pos (5U) +#define DDRPHYC_PGCR_DTOSEL_Msk (0xFU << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x000001E0 */ +#define DDRPHYC_PGCR_DTOSEL DDRPHYC_PGCR_DTOSEL_Msk /*!< Digital test output select */ +#define DDRPHYC_PGCR_DTOSEL_0 (0x1U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGCR_DTOSEL_1 (0x2U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGCR_DTOSEL_2 (0x4U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGCR_DTOSEL_3 (0x8U << DDRPHYC_PGCR_DTOSEL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGCR_CKEN_Pos (9U) +#define DDRPHYC_PGCR_CKEN_Msk (0x7U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_PGCR_CKEN DDRPHYC_PGCR_CKEN_Msk /*!< CK enable */ +#define DDRPHYC_PGCR_CKEN_0 (0x1U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGCR_CKEN_1 (0x2U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PGCR_CKEN_2 (0x4U << DDRPHYC_PGCR_CKEN_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PGCR_CKDV_Pos (12U) +#define DDRPHYC_PGCR_CKDV_Msk (0x3U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00003000 */ +#define DDRPHYC_PGCR_CKDV DDRPHYC_PGCR_CKDV_Msk /*!< CK disable value */ +#define DDRPHYC_PGCR_CKDV_0 (0x1U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PGCR_CKDV_1 (0x2U << DDRPHYC_PGCR_CKDV_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PGCR_CKINV_Pos (14U) +#define DDRPHYC_PGCR_CKINV_Msk (0x1U << DDRPHYC_PGCR_CKINV_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PGCR_CKINV DDRPHYC_PGCR_CKINV_Msk /*!< CK invert */ +#define DDRPHYC_PGCR_IOLB_Pos (15U) +#define DDRPHYC_PGCR_IOLB_Msk (0x1U << DDRPHYC_PGCR_IOLB_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PGCR_IOLB DDRPHYC_PGCR_IOLB_Msk /*!< I/O loop back select */ +#define DDRPHYC_PGCR_IODDRM_Pos (16U) +#define DDRPHYC_PGCR_IODDRM_Msk (0x3U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00030000 */ +#define DDRPHYC_PGCR_IODDRM DDRPHYC_PGCR_IODDRM_Msk /*!< I/O DDR mode */ +#define DDRPHYC_PGCR_IODDRM_0 (0x1U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PGCR_IODDRM_1 (0x2U << DDRPHYC_PGCR_IODDRM_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PGCR_RANKEN_Pos (18U) +#define DDRPHYC_PGCR_RANKEN_Msk (0xFU << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PGCR_RANKEN DDRPHYC_PGCR_RANKEN_Msk /*!< Rank enable */ +#define DDRPHYC_PGCR_RANKEN_0 (0x1U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PGCR_RANKEN_1 (0x2U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PGCR_RANKEN_2 (0x4U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PGCR_RANKEN_3 (0x8U << DDRPHYC_PGCR_RANKEN_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PGCR_ZKSEL_Pos (22U) +#define DDRPHYC_PGCR_ZKSEL_Msk (0x3U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00C00000 */ +#define DDRPHYC_PGCR_ZKSEL DDRPHYC_PGCR_ZKSEL_Msk /*!< Impedance clock divider selection */ +#define DDRPHYC_PGCR_ZKSEL_0 (0x1U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PGCR_ZKSEL_1 (0x2U << DDRPHYC_PGCR_ZKSEL_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PGCR_PDDISDX_Pos (24U) +#define DDRPHYC_PGCR_PDDISDX_Msk (0x1U << DDRPHYC_PGCR_PDDISDX_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PGCR_PDDISDX DDRPHYC_PGCR_PDDISDX_Msk /*!< Power down disabled byte */ +#define DDRPHYC_PGCR_RFSHDT_Pos (25U) +#define DDRPHYC_PGCR_RFSHDT_Msk (0xFU << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x1E000000 */ +#define DDRPHYC_PGCR_RFSHDT DDRPHYC_PGCR_RFSHDT_Msk /*!< Refresh during training */ +#define DDRPHYC_PGCR_RFSHDT_0 (0x1U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PGCR_RFSHDT_1 (0x2U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_PGCR_RFSHDT_2 (0x4U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x08000000 */ +#define DDRPHYC_PGCR_RFSHDT_3 (0x8U << DDRPHYC_PGCR_RFSHDT_Pos) /*!< 0x10000000 */ +#define DDRPHYC_PGCR_LBDQSS_Pos (29U) +#define DDRPHYC_PGCR_LBDQSS_Msk (0x1U << DDRPHYC_PGCR_LBDQSS_Pos) /*!< 0x20000000 */ +#define DDRPHYC_PGCR_LBDQSS DDRPHYC_PGCR_LBDQSS_Msk /*!< Loop back DQS shift */ +#define DDRPHYC_PGCR_LBGDQS_Pos (30U) +#define DDRPHYC_PGCR_LBGDQS_Msk (0x1U << DDRPHYC_PGCR_LBGDQS_Pos) /*!< 0x40000000 */ +#define DDRPHYC_PGCR_LBGDQS DDRPHYC_PGCR_LBGDQS_Msk /*!< Loop back DQS gating */ +#define DDRPHYC_PGCR_LBMODE_Pos (31U) +#define DDRPHYC_PGCR_LBMODE_Msk (0x1U << DDRPHYC_PGCR_LBMODE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGCR_LBMODE DDRPHYC_PGCR_LBMODE_Msk /*!< Loop back mode */ + +/***************** Bit definition for DDRPHYC_PGSR register *****************/ +#define DDRPHYC_PGSR_IDONE_Pos (0U) +#define DDRPHYC_PGSR_IDONE_Msk (0x1U << DDRPHYC_PGSR_IDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PGSR_IDONE DDRPHYC_PGSR_IDONE_Msk /*!< Initialization done */ +#define DDRPHYC_PGSR_DLDONE_Pos (1U) +#define DDRPHYC_PGSR_DLDONE_Msk (0x1U << DDRPHYC_PGSR_DLDONE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PGSR_DLDONE DDRPHYC_PGSR_DLDONE_Msk /*!< DLL lock done */ +#define DDRPHYC_PGSR_ZCDDONE_Pos (2U) +#define DDRPHYC_PGSR_ZCDDONE_Msk (0x1U << DDRPHYC_PGSR_ZCDDONE_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PGSR_ZCDDONE DDRPHYC_PGSR_ZCDDONE_Msk /*!< zcal done */ +#define DDRPHYC_PGSR_DIDONE_Pos (3U) +#define DDRPHYC_PGSR_DIDONE_Msk (0x1U << DDRPHYC_PGSR_DIDONE_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PGSR_DIDONE DDRPHYC_PGSR_DIDONE_Msk /*!< DRAM initialization done */ +#define DDRPHYC_PGSR_DTDONE_Pos (4U) +#define DDRPHYC_PGSR_DTDONE_Msk (0x1U << DDRPHYC_PGSR_DTDONE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PGSR_DTDONE DDRPHYC_PGSR_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_PGSR_DTERR_Pos (5U) +#define DDRPHYC_PGSR_DTERR_Msk (0x1U << DDRPHYC_PGSR_DTERR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PGSR_DTERR DDRPHYC_PGSR_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_PGSR_DTIERR_Pos (6U) +#define DDRPHYC_PGSR_DTIERR_Msk (0x1U << DDRPHYC_PGSR_DTIERR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PGSR_DTIERR DDRPHYC_PGSR_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_PGSR_DFTERR_Pos (7U) +#define DDRPHYC_PGSR_DFTERR_Msk (0x1U << DDRPHYC_PGSR_DFTERR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PGSR_DFTERR DDRPHYC_PGSR_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_PGSR_RVERR_Pos (8U) +#define DDRPHYC_PGSR_RVERR_Msk (0x1U << DDRPHYC_PGSR_RVERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PGSR_RVERR DDRPHYC_PGSR_RVERR_Msk /*!< Read valid training error */ +#define DDRPHYC_PGSR_RVEIRR_Pos (9U) +#define DDRPHYC_PGSR_RVEIRR_Msk (0x1U << DDRPHYC_PGSR_RVEIRR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PGSR_RVEIRR DDRPHYC_PGSR_RVEIRR_Msk /*!< Read valid training intermittent error */ +#define DDRPHYC_PGSR_TQ_Pos (31U) +#define DDRPHYC_PGSR_TQ_Msk (0x1U << DDRPHYC_PGSR_TQ_Pos) /*!< 0x80000000 */ +#define DDRPHYC_PGSR_TQ DDRPHYC_PGSR_TQ_Msk /*!< Temperature output (LPDDR only) N/A */ + +/**************** Bit definition for DDRPHYC_DLLGCR register ****************/ +#define DDRPHYC_DLLGCR_DRES_Pos (0U) +#define DDRPHYC_DLLGCR_DRES_Msk (0x3U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DLLGCR_DRES DDRPHYC_DLLGCR_DRES_Msk /*!< Trim reference current versus resistor value variation */ +#define DDRPHYC_DLLGCR_DRES_0 (0x1U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DLLGCR_DRES_1 (0x2U << DDRPHYC_DLLGCR_DRES_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DLLGCR_IPUMP_Pos (2U) +#define DDRPHYC_DLLGCR_IPUMP_Msk (0x7U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DLLGCR_IPUMP DDRPHYC_DLLGCR_IPUMP_Msk /*!< Charge pump current trim */ +#define DDRPHYC_DLLGCR_IPUMP_0 (0x1U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DLLGCR_IPUMP_1 (0x2U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DLLGCR_IPUMP_2 (0x4U << DDRPHYC_DLLGCR_IPUMP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DLLGCR_TESTEN_Pos (5U) +#define DDRPHYC_DLLGCR_TESTEN_Msk (0x1U << DDRPHYC_DLLGCR_TESTEN_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DLLGCR_TESTEN DDRPHYC_DLLGCR_TESTEN_Msk /*!< Test enable */ +#define DDRPHYC_DLLGCR_DTC_Pos (6U) +#define DDRPHYC_DLLGCR_DTC_Msk (0x7U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DLLGCR_DTC DDRPHYC_DLLGCR_DTC_Msk /*!< Digital test control */ +#define DDRPHYC_DLLGCR_DTC_0 (0x1U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DLLGCR_DTC_1 (0x2U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DLLGCR_DTC_2 (0x4U << DDRPHYC_DLLGCR_DTC_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DLLGCR_ATC_Pos (9U) +#define DDRPHYC_DLLGCR_ATC_Msk (0x3U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DLLGCR_ATC DDRPHYC_DLLGCR_ATC_Msk /*!< Analog test control */ +#define DDRPHYC_DLLGCR_ATC_0 (0x1U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DLLGCR_ATC_1 (0x2U << DDRPHYC_DLLGCR_ATC_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DLLGCR_TESTSW_Pos (11U) +#define DDRPHYC_DLLGCR_TESTSW_Msk (0x1U << DDRPHYC_DLLGCR_TESTSW_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DLLGCR_TESTSW DDRPHYC_DLLGCR_TESTSW_Msk /*!< Test switch */ +#define DDRPHYC_DLLGCR_MBIAS_Pos (12U) +#define DDRPHYC_DLLGCR_MBIAS_Msk (0xFFU << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x000FF000 */ +#define DDRPHYC_DLLGCR_MBIAS DDRPHYC_DLLGCR_MBIAS_Msk /*!< Master bias trim */ +#define DDRPHYC_DLLGCR_MBIAS_0 (0x1U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DLLGCR_MBIAS_1 (0x2U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DLLGCR_MBIAS_2 (0x4U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DLLGCR_MBIAS_3 (0x8U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DLLGCR_MBIAS_4 (0x10U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DLLGCR_MBIAS_5 (0x20U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DLLGCR_MBIAS_6 (0x40U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DLLGCR_MBIAS_7 (0x80U << DDRPHYC_DLLGCR_MBIAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_Pos (20U) +#define DDRPHYC_DLLGCR_SBIAS2_0_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0 DDRPHYC_DLLGCR_SBIAS2_0_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS2_0_0 (0x1U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_1 (0x2U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DLLGCR_SBIAS2_0_2 (0x4U << DDRPHYC_DLLGCR_SBIAS2_0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DLLGCR_BPS200_Pos (23U) +#define DDRPHYC_DLLGCR_BPS200_Msk (0x1U << DDRPHYC_DLLGCR_BPS200_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DLLGCR_BPS200 DDRPHYC_DLLGCR_BPS200_Msk /*!< Bypass mode frequency range */ +#define DDRPHYC_DLLGCR_SBIAS5_3_Pos (24U) +#define DDRPHYC_DLLGCR_SBIAS5_3_Msk (0x7U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3 DDRPHYC_DLLGCR_SBIAS5_3_Msk /*!< Slave bias trim */ +#define DDRPHYC_DLLGCR_SBIAS5_3_0 (0x1U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_1 (0x2U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DLLGCR_SBIAS5_3_2 (0x4U << DDRPHYC_DLLGCR_SBIAS5_3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_Pos (27U) +#define DDRPHYC_DLLGCR_FDTRMSL_Msk (0x3U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x18000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL DDRPHYC_DLLGCR_FDTRMSL_Msk /*!< Slave bypass fixed delay trim */ +#define DDRPHYC_DLLGCR_FDTRMSL_0 (0x1U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DLLGCR_FDTRMSL_1 (0x2U << DDRPHYC_DLLGCR_FDTRMSL_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DLLGCR_LOCKDET_Pos (29U) +#define DDRPHYC_DLLGCR_LOCKDET_Msk (0x1U << DDRPHYC_DLLGCR_LOCKDET_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DLLGCR_LOCKDET DDRPHYC_DLLGCR_LOCKDET_Msk /*!< Master lock detect enable */ +#define DDRPHYC_DLLGCR_DLLRSVD2_Pos (30U) +#define DDRPHYC_DLLGCR_DLLRSVD2_Msk (0x3U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2 DDRPHYC_DLLGCR_DLLRSVD2_Msk /*!< These bit are connected to the DLL control bus and reserved for future use. */ +#define DDRPHYC_DLLGCR_DLLRSVD2_0 (0x1U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DLLGCR_DLLRSVD2_1 (0x2U << DDRPHYC_DLLGCR_DLLRSVD2_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_ACDLLCR register ****************/ +#define DDRPHYC_ACDLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_ACDLLCR_MFBDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back delay trim */ +#define DDRPHYC_ACDLLCR_MFBDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACDLLCR_MFBDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACDLLCR_MFBDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACDLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_ACDLLCR_MFWDLY_Msk (0x7U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forward delay trim */ +#define DDRPHYC_ACDLLCR_MFWDLY_0 (0x1U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACDLLCR_MFWDLY_1 (0x2U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACDLLCR_MFWDLY_2 (0x4U << DDRPHYC_ACDLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACDLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_ACDLLCR_ATESTEN_Msk (0x1U << DDRPHYC_ACDLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACDLLCR_ATESTEN DDRPHYC_ACDLLCR_ATESTEN_Msk /*!< Analog test enable */ +#define DDRPHYC_ACDLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_ACDLLCR_DLLSRST_Msk (0x1U << DDRPHYC_ACDLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACDLLCR_DLLSRST DDRPHYC_ACDLLCR_DLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_ACDLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_ACDLLCR_DLLDIS_Msk (0x1U << DDRPHYC_ACDLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ACDLLCR_DLLDIS DDRPHYC_ACDLLCR_DLLDIS_Msk /*!< DLL disable */ + +/***************** Bit definition for DDRPHYC_PTR0 register *****************/ +#define DDRPHYC_PTR0_TDLLSRST_Pos (0U) +#define DDRPHYC_PTR0_TDLLSRST_Msk (0x3FU << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x0000003F */ +#define DDRPHYC_PTR0_TDLLSRST DDRPHYC_PTR0_TDLLSRST_Msk /*!< DLL soft reset */ +#define DDRPHYC_PTR0_TDLLSRST_0 (0x1U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR0_TDLLSRST_1 (0x2U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR0_TDLLSRST_2 (0x4U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR0_TDLLSRST_3 (0x8U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR0_TDLLSRST_4 (0x10U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR0_TDLLSRST_5 (0x20U << DDRPHYC_PTR0_TDLLSRST_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR0_TDLLLOCK_Pos (6U) +#define DDRPHYC_PTR0_TDLLLOCK_Msk (0xFFFU << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x0003FFC0 */ +#define DDRPHYC_PTR0_TDLLLOCK DDRPHYC_PTR0_TDLLLOCK_Msk /*!< DLL lock time */ +#define DDRPHYC_PTR0_TDLLLOCK_0 (0x1U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR0_TDLLLOCK_1 (0x2U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR0_TDLLLOCK_2 (0x4U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR0_TDLLLOCK_3 (0x8U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR0_TDLLLOCK_4 (0x10U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR0_TDLLLOCK_5 (0x20U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR0_TDLLLOCK_6 (0x40U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR0_TDLLLOCK_7 (0x80U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR0_TDLLLOCK_8 (0x100U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR0_TDLLLOCK_9 (0x200U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR0_TDLLLOCK_10 (0x400U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR0_TDLLLOCK_11 (0x800U << DDRPHYC_PTR0_TDLLLOCK_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR0_TITMSRST_Pos (18U) +#define DDRPHYC_PTR0_TITMSRST_Msk (0xFU << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x003C0000 */ +#define DDRPHYC_PTR0_TITMSRST DDRPHYC_PTR0_TITMSRST_Msk /*!< ITM soft reset */ +#define DDRPHYC_PTR0_TITMSRST_0 (0x1U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR0_TITMSRST_1 (0x2U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR0_TITMSRST_2 (0x4U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR0_TITMSRST_3 (0x8U << DDRPHYC_PTR0_TITMSRST_Pos) /*!< 0x00200000 */ + +/***************** Bit definition for DDRPHYC_PTR1 register *****************/ +#define DDRPHYC_PTR1_TDINIT0_Pos (0U) +#define DDRPHYC_PTR1_TDINIT0_Msk (0x7FFFFU << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x0007FFFF */ +#define DDRPHYC_PTR1_TDINIT0 DDRPHYC_PTR1_TDINIT0_Msk /*!< tDINIT0 */ +#define DDRPHYC_PTR1_TDINIT0_0 (0x1U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR1_TDINIT0_1 (0x2U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR1_TDINIT0_2 (0x4U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR1_TDINIT0_3 (0x8U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR1_TDINIT0_4 (0x10U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR1_TDINIT0_5 (0x20U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR1_TDINIT0_6 (0x40U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR1_TDINIT0_7 (0x80U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR1_TDINIT0_8 (0x100U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR1_TDINIT0_9 (0x200U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR1_TDINIT0_10 (0x400U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR1_TDINIT0_11 (0x800U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR1_TDINIT0_12 (0x1000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR1_TDINIT0_13 (0x2000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR1_TDINIT0_14 (0x4000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR1_TDINIT0_15 (0x8000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR1_TDINIT0_16 (0x10000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR1_TDINIT0_17 (0x20000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR1_TDINIT0_18 (0x40000U << DDRPHYC_PTR1_TDINIT0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR1_TDINIT1_Pos (19U) +#define DDRPHYC_PTR1_TDINIT1_Msk (0xFFU << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x07F80000 */ +#define DDRPHYC_PTR1_TDINIT1 DDRPHYC_PTR1_TDINIT1_Msk /*!< tDINIT1 */ +#define DDRPHYC_PTR1_TDINIT1_0 (0x1U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR1_TDINIT1_1 (0x2U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR1_TDINIT1_2 (0x4U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR1_TDINIT1_3 (0x8U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR1_TDINIT1_4 (0x10U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR1_TDINIT1_5 (0x20U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR1_TDINIT1_6 (0x40U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR1_TDINIT1_7 (0x80U << DDRPHYC_PTR1_TDINIT1_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for DDRPHYC_PTR2 register *****************/ +#define DDRPHYC_PTR2_TDINIT2_Pos (0U) +#define DDRPHYC_PTR2_TDINIT2_Msk (0x1FFFFU << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x0001FFFF */ +#define DDRPHYC_PTR2_TDINIT2 DDRPHYC_PTR2_TDINIT2_Msk /*!< tDINIT2 */ +#define DDRPHYC_PTR2_TDINIT2_0 (0x1U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000001 */ +#define DDRPHYC_PTR2_TDINIT2_1 (0x2U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000002 */ +#define DDRPHYC_PTR2_TDINIT2_2 (0x4U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000004 */ +#define DDRPHYC_PTR2_TDINIT2_3 (0x8U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000008 */ +#define DDRPHYC_PTR2_TDINIT2_4 (0x10U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000010 */ +#define DDRPHYC_PTR2_TDINIT2_5 (0x20U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000020 */ +#define DDRPHYC_PTR2_TDINIT2_6 (0x40U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000040 */ +#define DDRPHYC_PTR2_TDINIT2_7 (0x80U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000080 */ +#define DDRPHYC_PTR2_TDINIT2_8 (0x100U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_PTR2_TDINIT2_9 (0x200U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_PTR2_TDINIT2_10 (0x400U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_PTR2_TDINIT2_11 (0x800U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_PTR2_TDINIT2_12 (0x1000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00001000 */ +#define DDRPHYC_PTR2_TDINIT2_13 (0x2000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00002000 */ +#define DDRPHYC_PTR2_TDINIT2_14 (0x4000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00004000 */ +#define DDRPHYC_PTR2_TDINIT2_15 (0x8000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00008000 */ +#define DDRPHYC_PTR2_TDINIT2_16 (0x10000U << DDRPHYC_PTR2_TDINIT2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_PTR2_TDINIT3_Pos (17U) +#define DDRPHYC_PTR2_TDINIT3_Msk (0x3FFU << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x07FE0000 */ +#define DDRPHYC_PTR2_TDINIT3 DDRPHYC_PTR2_TDINIT3_Msk /*!< tDINIT3 */ +#define DDRPHYC_PTR2_TDINIT3_0 (0x1U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00020000 */ +#define DDRPHYC_PTR2_TDINIT3_1 (0x2U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00040000 */ +#define DDRPHYC_PTR2_TDINIT3_2 (0x4U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00080000 */ +#define DDRPHYC_PTR2_TDINIT3_3 (0x8U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00100000 */ +#define DDRPHYC_PTR2_TDINIT3_4 (0x10U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00200000 */ +#define DDRPHYC_PTR2_TDINIT3_5 (0x20U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00400000 */ +#define DDRPHYC_PTR2_TDINIT3_6 (0x40U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x00800000 */ +#define DDRPHYC_PTR2_TDINIT3_7 (0x80U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_PTR2_TDINIT3_8 (0x100U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_PTR2_TDINIT3_9 (0x200U << DDRPHYC_PTR2_TDINIT3_Pos) /*!< 0x04000000 */ + +/**************** Bit definition for DDRPHYC_ACIOCR register ****************/ +#define DDRPHYC_ACIOCR_ACIOM_Pos (0U) +#define DDRPHYC_ACIOCR_ACIOM_Msk (0x1U << DDRPHYC_ACIOCR_ACIOM_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ACIOCR_ACIOM DDRPHYC_ACIOCR_ACIOM_Msk /*!< AC pins I/O mode */ +#define DDRPHYC_ACIOCR_ACOE_Pos (1U) +#define DDRPHYC_ACIOCR_ACOE_Msk (0x1U << DDRPHYC_ACIOCR_ACOE_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ACIOCR_ACOE DDRPHYC_ACIOCR_ACOE_Msk /*!< AC pins output enable */ +#define DDRPHYC_ACIOCR_ACODT_Pos (2U) +#define DDRPHYC_ACIOCR_ACODT_Msk (0x1U << DDRPHYC_ACIOCR_ACODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ACIOCR_ACODT DDRPHYC_ACIOCR_ACODT_Msk /*!< AC pins ODT */ +#define DDRPHYC_ACIOCR_ACPDD_Pos (3U) +#define DDRPHYC_ACIOCR_ACPDD_Msk (0x1U << DDRPHYC_ACIOCR_ACPDD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ACIOCR_ACPDD DDRPHYC_ACIOCR_ACPDD_Msk /*!< AC pins power down drivers */ +#define DDRPHYC_ACIOCR_ACPDR_Pos (4U) +#define DDRPHYC_ACIOCR_ACPDR_Msk (0x1U << DDRPHYC_ACIOCR_ACPDR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ACIOCR_ACPDR DDRPHYC_ACIOCR_ACPDR_Msk /*!< AC pins power down receivers */ +#define DDRPHYC_ACIOCR_CKODT_Pos (5U) +#define DDRPHYC_ACIOCR_CKODT_Msk (0x7U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_ACIOCR_CKODT DDRPHYC_ACIOCR_CKODT_Msk /*!< CK pin ODT */ +#define DDRPHYC_ACIOCR_CKODT_0 (0x1U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ACIOCR_CKODT_1 (0x2U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ACIOCR_CKODT_2 (0x4U << DDRPHYC_ACIOCR_CKODT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ACIOCR_CKPDD_Pos (8U) +#define DDRPHYC_ACIOCR_CKPDD_Msk (0x7U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000700 */ +#define DDRPHYC_ACIOCR_CKPDD DDRPHYC_ACIOCR_CKPDD_Msk /*!< CK pin power down driver */ +#define DDRPHYC_ACIOCR_CKPDD_0 (0x1U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ACIOCR_CKPDD_1 (0x2U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ACIOCR_CKPDD_2 (0x4U << DDRPHYC_ACIOCR_CKPDD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ACIOCR_CKPDR_Pos (11U) +#define DDRPHYC_ACIOCR_CKPDR_Msk (0x7U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00003800 */ +#define DDRPHYC_ACIOCR_CKPDR DDRPHYC_ACIOCR_CKPDR_Msk /*!< CK pin power down receiver */ +#define DDRPHYC_ACIOCR_CKPDR_0 (0x1U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ACIOCR_CKPDR_1 (0x2U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ACIOCR_CKPDR_2 (0x4U << DDRPHYC_ACIOCR_CKPDR_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ACIOCR_RANKODT_Pos (14U) +#define DDRPHYC_ACIOCR_RANKODT_Msk (0x1U << DDRPHYC_ACIOCR_RANKODT_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ACIOCR_RANKODT DDRPHYC_ACIOCR_RANKODT_Msk /*!< Rank ODT */ +#define DDRPHYC_ACIOCR_CSPDD_Pos (18U) +#define DDRPHYC_ACIOCR_CSPDD_Msk (0x1U << DDRPHYC_ACIOCR_CSPDD_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ACIOCR_CSPDD DDRPHYC_ACIOCR_CSPDD_Msk /*!< CS power down driver */ +#define DDRPHYC_ACIOCR_RANKPDR_Pos (22U) +#define DDRPHYC_ACIOCR_RANKPDR_Msk (0x1U << DDRPHYC_ACIOCR_RANKPDR_Pos) /*!< 0x00400000 */ +#define DDRPHYC_ACIOCR_RANKPDR DDRPHYC_ACIOCR_RANKPDR_Msk /*!< Rank power down receiver */ +#define DDRPHYC_ACIOCR_RSTODT_Pos (26U) +#define DDRPHYC_ACIOCR_RSTODT_Msk (0x1U << DDRPHYC_ACIOCR_RSTODT_Pos) /*!< 0x04000000 */ +#define DDRPHYC_ACIOCR_RSTODT DDRPHYC_ACIOCR_RSTODT_Msk /*!< RST pin ODT */ +#define DDRPHYC_ACIOCR_RSTPDD_Pos (27U) +#define DDRPHYC_ACIOCR_RSTPDD_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDD_Pos) /*!< 0x08000000 */ +#define DDRPHYC_ACIOCR_RSTPDD DDRPHYC_ACIOCR_RSTPDD_Msk /*!< RST pin power down driver */ +#define DDRPHYC_ACIOCR_RSTPDR_Pos (28U) +#define DDRPHYC_ACIOCR_RSTPDR_Msk (0x1U << DDRPHYC_ACIOCR_RSTPDR_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ACIOCR_RSTPDR DDRPHYC_ACIOCR_RSTPDR_Msk /*!< RST pin power down receiver */ +#define DDRPHYC_ACIOCR_RSTIOM_Pos (29U) +#define DDRPHYC_ACIOCR_RSTIOM_Msk (0x1U << DDRPHYC_ACIOCR_RSTIOM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ACIOCR_RSTIOM DDRPHYC_ACIOCR_RSTIOM_Msk /*!< Reset I/O mode */ +#define DDRPHYC_ACIOCR_ACSR_Pos (30U) +#define DDRPHYC_ACIOCR_ACSR_Msk (0x3U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0xC0000000 */ +#define DDRPHYC_ACIOCR_ACSR DDRPHYC_ACIOCR_ACSR_Msk /*!< AC slew rate */ +#define DDRPHYC_ACIOCR_ACSR_0 (0x1U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ACIOCR_ACSR_1 (0x2U << DDRPHYC_ACIOCR_ACSR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DXCCR register *****************/ +#define DDRPHYC_DXCCR_DXODT_Pos (0U) +#define DDRPHYC_DXCCR_DXODT_Msk (0x1U << DDRPHYC_DXCCR_DXODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DXCCR_DXODT DDRPHYC_DXCCR_DXODT_Msk /*!< Data on die termination */ +#define DDRPHYC_DXCCR_DXIOM_Pos (1U) +#define DDRPHYC_DXCCR_DXIOM_Msk (0x1U << DDRPHYC_DXCCR_DXIOM_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DXCCR_DXIOM DDRPHYC_DXCCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DXCCR_DXPDD_Pos (2U) +#define DDRPHYC_DXCCR_DXPDD_Msk (0x1U << DDRPHYC_DXCCR_DXPDD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DXCCR_DXPDD DDRPHYC_DXCCR_DXPDD_Msk /*!< Data power down driver */ +#define DDRPHYC_DXCCR_DXPDR_Pos (3U) +#define DDRPHYC_DXCCR_DXPDR_Msk (0x1U << DDRPHYC_DXCCR_DXPDR_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DXCCR_DXPDR DDRPHYC_DXCCR_DXPDR_Msk /*!< Data power down receiver */ +#define DDRPHYC_DXCCR_DQSRES_Pos (4U) +#define DDRPHYC_DXCCR_DQSRES_Msk (0xFU << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DXCCR_DQSRES DDRPHYC_DXCCR_DQSRES_Msk /*!< DQS resistor */ +#define DDRPHYC_DXCCR_DQSRES_0 (0x1U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DXCCR_DQSRES_1 (0x2U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DXCCR_DQSRES_2 (0x4U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DXCCR_DQSRES_3 (0x8U << DDRPHYC_DXCCR_DQSRES_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DXCCR_DQSNRES_Pos (8U) +#define DDRPHYC_DXCCR_DQSNRES_Msk (0xFU << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DXCCR_DQSNRES DDRPHYC_DXCCR_DQSNRES_Msk /*!< DQS# resistor */ +#define DDRPHYC_DXCCR_DQSNRES_0 (0x1U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DXCCR_DQSNRES_1 (0x2U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DXCCR_DQSNRES_2 (0x4U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DXCCR_DQSNRES_3 (0x8U << DDRPHYC_DXCCR_DQSNRES_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DXCCR_DQSNRST_Pos (14U) +#define DDRPHYC_DXCCR_DQSNRST_Msk (0x1U << DDRPHYC_DXCCR_DQSNRST_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DXCCR_DQSNRST DDRPHYC_DXCCR_DQSNRST_Msk /*!< DQS reset */ +#define DDRPHYC_DXCCR_RVSEL_Pos (15U) +#define DDRPHYC_DXCCR_RVSEL_Msk (0x1U << DDRPHYC_DXCCR_RVSEL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DXCCR_RVSEL DDRPHYC_DXCCR_RVSEL_Msk /*!< ITMD read valid select */ +#define DDRPHYC_DXCCR_AWDT_Pos (16U) +#define DDRPHYC_DXCCR_AWDT_Msk (0x1U << DDRPHYC_DXCCR_AWDT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DXCCR_AWDT DDRPHYC_DXCCR_AWDT_Msk /*!< Active window data train */ + +/**************** Bit definition for DDRPHYC_DSGCR register *****************/ +#define DDRPHYC_DSGCR_PUREN_Pos (0U) +#define DDRPHYC_DSGCR_PUREN_Msk (0x1U << DDRPHYC_DSGCR_PUREN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DSGCR_PUREN DDRPHYC_DSGCR_PUREN_Msk /*!< PHY update request enable */ +#define DDRPHYC_DSGCR_BDISEN_Pos (1U) +#define DDRPHYC_DSGCR_BDISEN_Msk (0x1U << DDRPHYC_DSGCR_BDISEN_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DSGCR_BDISEN DDRPHYC_DSGCR_BDISEN_Msk /*!< Byte disable enable */ +#define DDRPHYC_DSGCR_ZUEN_Pos (2U) +#define DDRPHYC_DSGCR_ZUEN_Msk (0x1U << DDRPHYC_DSGCR_ZUEN_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DSGCR_ZUEN DDRPHYC_DSGCR_ZUEN_Msk /*!< zcal on DFI update request */ +#define DDRPHYC_DSGCR_LPIOPD_Pos (3U) +#define DDRPHYC_DSGCR_LPIOPD_Msk (0x1U << DDRPHYC_DSGCR_LPIOPD_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DSGCR_LPIOPD DDRPHYC_DSGCR_LPIOPD_Msk /*!< Low power I/O power down */ +#define DDRPHYC_DSGCR_LPDLLPD_Pos (4U) +#define DDRPHYC_DSGCR_LPDLLPD_Msk (0x1U << DDRPHYC_DSGCR_LPDLLPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DSGCR_LPDLLPD DDRPHYC_DSGCR_LPDLLPD_Msk /*!< Low power DLL power down */ +#define DDRPHYC_DSGCR_DQSGX_Pos (5U) +#define DDRPHYC_DSGCR_DQSGX_Msk (0x7U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DSGCR_DQSGX DDRPHYC_DSGCR_DQSGX_Msk /*!< DQS gate extension */ +#define DDRPHYC_DSGCR_DQSGX_0 (0x1U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DSGCR_DQSGX_1 (0x2U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DSGCR_DQSGX_2 (0x4U << DDRPHYC_DSGCR_DQSGX_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DSGCR_DQSGE_Pos (8U) +#define DDRPHYC_DSGCR_DQSGE_Msk (0x7U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000700 */ +#define DDRPHYC_DSGCR_DQSGE DDRPHYC_DSGCR_DQSGE_Msk /*!< DQS gate early */ +#define DDRPHYC_DSGCR_DQSGE_0 (0x1U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DSGCR_DQSGE_1 (0x2U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DSGCR_DQSGE_2 (0x4U << DDRPHYC_DSGCR_DQSGE_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DSGCR_NOBUB_Pos (11U) +#define DDRPHYC_DSGCR_NOBUB_Msk (0x1U << DDRPHYC_DSGCR_NOBUB_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DSGCR_NOBUB DDRPHYC_DSGCR_NOBUB_Msk /*!< No bubble */ +#define DDRPHYC_DSGCR_FXDLAT_Pos (12U) +#define DDRPHYC_DSGCR_FXDLAT_Msk (0x1U << DDRPHYC_DSGCR_FXDLAT_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DSGCR_FXDLAT DDRPHYC_DSGCR_FXDLAT_Msk /*!< Fixed latency */ +#define DDRPHYC_DSGCR_CKEPDD_Pos (16U) +#define DDRPHYC_DSGCR_CKEPDD_Msk (0x1U << DDRPHYC_DSGCR_CKEPDD_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DSGCR_CKEPDD DDRPHYC_DSGCR_CKEPDD_Msk /*!< CKE power down driver */ +#define DDRPHYC_DSGCR_ODTPDD_Pos (20U) +#define DDRPHYC_DSGCR_ODTPDD_Msk (0x1U << DDRPHYC_DSGCR_ODTPDD_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DSGCR_ODTPDD DDRPHYC_DSGCR_ODTPDD_Msk /*!< ODT power down driver */ +#define DDRPHYC_DSGCR_NL2PD_Pos (24U) +#define DDRPHYC_DSGCR_NL2PD_Msk (0x1U << DDRPHYC_DSGCR_NL2PD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DSGCR_NL2PD DDRPHYC_DSGCR_NL2PD_Msk /*!< Non LPDDR2 power down */ +#define DDRPHYC_DSGCR_NL2OE_Pos (25U) +#define DDRPHYC_DSGCR_NL2OE_Msk (0x1U << DDRPHYC_DSGCR_NL2OE_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DSGCR_NL2OE DDRPHYC_DSGCR_NL2OE_Msk /*!< Non LPDDR2 output enable */ +#define DDRPHYC_DSGCR_TPDPD_Pos (26U) +#define DDRPHYC_DSGCR_TPDPD_Msk (0x1U << DDRPHYC_DSGCR_TPDPD_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DSGCR_TPDPD DDRPHYC_DSGCR_TPDPD_Msk /*!< TPD power down driver (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_TPDOE_Pos (27U) +#define DDRPHYC_DSGCR_TPDOE_Msk (0x1U << DDRPHYC_DSGCR_TPDOE_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DSGCR_TPDOE DDRPHYC_DSGCR_TPDOE_Msk /*!< TPD output enable (N/A LPDDR only) */ +#define DDRPHYC_DSGCR_CKOE_Pos (28U) +#define DDRPHYC_DSGCR_CKOE_Msk (0x1U << DDRPHYC_DSGCR_CKOE_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DSGCR_CKOE DDRPHYC_DSGCR_CKOE_Msk /*!< CK output enable */ +#define DDRPHYC_DSGCR_ODTOE_Pos (29U) +#define DDRPHYC_DSGCR_ODTOE_Msk (0x1U << DDRPHYC_DSGCR_ODTOE_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DSGCR_ODTOE DDRPHYC_DSGCR_ODTOE_Msk /*!< ODT output enable */ +#define DDRPHYC_DSGCR_RSTOE_Pos (30U) +#define DDRPHYC_DSGCR_RSTOE_Msk (0x1U << DDRPHYC_DSGCR_RSTOE_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DSGCR_RSTOE DDRPHYC_DSGCR_RSTOE_Msk /*!< RST output enable */ +#define DDRPHYC_DSGCR_CKEOE_Pos (31U) +#define DDRPHYC_DSGCR_CKEOE_Msk (0x1U << DDRPHYC_DSGCR_CKEOE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DSGCR_CKEOE DDRPHYC_DSGCR_CKEOE_Msk /*!< CKE output enable */ + +/***************** Bit definition for DDRPHYC_DCR register ******************/ +#define DDRPHYC_DCR_DDRMD_Pos (0U) +#define DDRPHYC_DCR_DDRMD_Msk (0x7U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DCR_DDRMD DDRPHYC_DCR_DDRMD_Msk /*!< SDRAM DDR mode */ +#define DDRPHYC_DCR_DDRMD_0 (0x1U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DCR_DDRMD_1 (0x2U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DCR_DDRMD_2 (0x4U << DDRPHYC_DCR_DDRMD_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DCR_DDR8BNK_Pos (3U) +#define DDRPHYC_DCR_DDR8BNK_Msk (0x1U << DDRPHYC_DCR_DDR8BNK_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DCR_DDR8BNK DDRPHYC_DCR_DDR8BNK_Msk /*!< DDR 8 banks */ +#define DDRPHYC_DCR_PDQ_Pos (4U) +#define DDRPHYC_DCR_PDQ_Msk (0x7U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DCR_PDQ DDRPHYC_DCR_PDQ_Msk /*!< Primary DQ(DDR3 Only) */ +#define DDRPHYC_DCR_PDQ_0 (0x1U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DCR_PDQ_1 (0x2U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DCR_PDQ_2 (0x4U << DDRPHYC_DCR_PDQ_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DCR_MPRDQ_Pos (7U) +#define DDRPHYC_DCR_MPRDQ_Msk (0x1U << DDRPHYC_DCR_MPRDQ_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DCR_MPRDQ DDRPHYC_DCR_MPRDQ_Msk /*!< MPR DQ */ +#define DDRPHYC_DCR_DDRTYPE_Pos (8U) +#define DDRPHYC_DCR_DDRTYPE_Msk (0x3U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000300 */ +#define DDRPHYC_DCR_DDRTYPE DDRPHYC_DCR_DDRTYPE_Msk /*!< DDR type (LPDDR2 S4) */ +#define DDRPHYC_DCR_DDRTYPE_0 (0x1U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DCR_DDRTYPE_1 (0x2U << DDRPHYC_DCR_DDRTYPE_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DCR_NOSRA_Pos (27U) +#define DDRPHYC_DCR_NOSRA_Msk (0x1U << DDRPHYC_DCR_NOSRA_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DCR_NOSRA DDRPHYC_DCR_NOSRA_Msk /*!< No simultaneous rank access */ +#define DDRPHYC_DCR_DDR2T_Pos (28U) +#define DDRPHYC_DCR_DDR2T_Msk (0x1U << DDRPHYC_DCR_DDR2T_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DCR_DDR2T DDRPHYC_DCR_DDR2T_Msk /*!< 2T timing */ +#define DDRPHYC_DCR_UDIMM_Pos (29U) +#define DDRPHYC_DCR_UDIMM_Msk (0x1U << DDRPHYC_DCR_UDIMM_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DCR_UDIMM DDRPHYC_DCR_UDIMM_Msk /*!< Unbuffered DIMM */ +#define DDRPHYC_DCR_RDIMM_Pos (30U) +#define DDRPHYC_DCR_RDIMM_Msk (0x1U << DDRPHYC_DCR_RDIMM_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DCR_RDIMM DDRPHYC_DCR_RDIMM_Msk /*!< Registered DIMM */ +#define DDRPHYC_DCR_TPD_Pos (31U) +#define DDRPHYC_DCR_TPD_Msk (0x1U << DDRPHYC_DCR_TPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DCR_TPD DDRPHYC_DCR_TPD_Msk /*!< Test power down (N/A LPDDR only) */ + +/**************** Bit definition for DDRPHYC_DTPR0 register *****************/ +#define DDRPHYC_DTPR0_TMRD_Pos (0U) +#define DDRPHYC_DTPR0_TMRD_Msk (0x3U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR0_TMRD DDRPHYC_DTPR0_TMRD_Msk /*!< tMRD */ +#define DDRPHYC_DTPR0_TMRD_0 (0x1U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR0_TMRD_1 (0x2U << DDRPHYC_DTPR0_TMRD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR0_TRTP_Pos (2U) +#define DDRPHYC_DTPR0_TRTP_Msk (0x7U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x0000001C */ +#define DDRPHYC_DTPR0_TRTP DDRPHYC_DTPR0_TRTP_Msk /*!< tRTP */ +#define DDRPHYC_DTPR0_TRTP_0 (0x1U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR0_TRTP_1 (0x2U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR0_TRTP_2 (0x4U << DDRPHYC_DTPR0_TRTP_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR0_TWTR_Pos (5U) +#define DDRPHYC_DTPR0_TWTR_Msk (0x7U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DTPR0_TWTR DDRPHYC_DTPR0_TWTR_Msk /*!< tWTR */ +#define DDRPHYC_DTPR0_TWTR_0 (0x1U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR0_TWTR_1 (0x2U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR0_TWTR_2 (0x4U << DDRPHYC_DTPR0_TWTR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR0_TRP_Pos (8U) +#define DDRPHYC_DTPR0_TRP_Msk (0xFU << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DTPR0_TRP DDRPHYC_DTPR0_TRP_Msk /*!< tRP */ +#define DDRPHYC_DTPR0_TRP_0 (0x1U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR0_TRP_1 (0x2U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR0_TRP_2 (0x4U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR0_TRP_3 (0x8U << DDRPHYC_DTPR0_TRP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR0_TRCD_Pos (12U) +#define DDRPHYC_DTPR0_TRCD_Msk (0xFU << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DTPR0_TRCD DDRPHYC_DTPR0_TRCD_Msk /*!< tRCD */ +#define DDRPHYC_DTPR0_TRCD_0 (0x1U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR0_TRCD_1 (0x2U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR0_TRCD_2 (0x4U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR0_TRCD_3 (0x8U << DDRPHYC_DTPR0_TRCD_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR0_TRAS_Pos (16U) +#define DDRPHYC_DTPR0_TRAS_Msk (0x1FU << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x001F0000 */ +#define DDRPHYC_DTPR0_TRAS DDRPHYC_DTPR0_TRAS_Msk /*!< tRAS */ +#define DDRPHYC_DTPR0_TRAS_0 (0x1U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR0_TRAS_1 (0x2U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR0_TRAS_2 (0x4U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR0_TRAS_3 (0x8U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR0_TRAS_4 (0x10U << DDRPHYC_DTPR0_TRAS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR0_TRRD_Pos (21U) +#define DDRPHYC_DTPR0_TRRD_Msk (0xFU << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01E00000 */ +#define DDRPHYC_DTPR0_TRRD DDRPHYC_DTPR0_TRRD_Msk /*!< tRRD */ +#define DDRPHYC_DTPR0_TRRD_0 (0x1U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR0_TRRD_1 (0x2U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR0_TRRD_2 (0x4U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR0_TRRD_3 (0x8U << DDRPHYC_DTPR0_TRRD_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR0_TRC_Pos (25U) +#define DDRPHYC_DTPR0_TRC_Msk (0x3FU << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x7E000000 */ +#define DDRPHYC_DTPR0_TRC DDRPHYC_DTPR0_TRC_Msk /*!< tRC */ +#define DDRPHYC_DTPR0_TRC_0 (0x1U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR0_TRC_1 (0x2U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR0_TRC_2 (0x4U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR0_TRC_3 (0x8U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR0_TRC_4 (0x10U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTPR0_TRC_5 (0x20U << DDRPHYC_DTPR0_TRC_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTPR0_TCCD_Pos (31U) +#define DDRPHYC_DTPR0_TCCD_Msk (0x1U << DDRPHYC_DTPR0_TCCD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTPR0_TCCD DDRPHYC_DTPR0_TCCD_Msk /*!< tCCDRead to read and write to write command delay */ + +/**************** Bit definition for DDRPHYC_DTPR1 register *****************/ +#define DDRPHYC_DTPR1_TAOND_Pos (0U) +#define DDRPHYC_DTPR1_TAOND_Msk (0x3U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DTPR1_TAOND DDRPHYC_DTPR1_TAOND_Msk /*!< tAOND/tAOFD */ +#define DDRPHYC_DTPR1_TAOND_0 (0x1U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR1_TAOND_1 (0x2U << DDRPHYC_DTPR1_TAOND_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR1_TRTW_Pos (2U) +#define DDRPHYC_DTPR1_TRTW_Msk (0x1U << DDRPHYC_DTPR1_TRTW_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR1_TRTW DDRPHYC_DTPR1_TRTW_Msk /*!< tRTW */ +#define DDRPHYC_DTPR1_TFAW_Pos (3U) +#define DDRPHYC_DTPR1_TFAW_Msk (0x3FU << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x000001F8 */ +#define DDRPHYC_DTPR1_TFAW DDRPHYC_DTPR1_TFAW_Msk /*!< tFAW */ +#define DDRPHYC_DTPR1_TFAW_0 (0x1U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR1_TFAW_1 (0x2U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR1_TFAW_2 (0x4U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR1_TFAW_3 (0x8U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR1_TFAW_4 (0x10U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR1_TFAW_5 (0x20U << DDRPHYC_DTPR1_TFAW_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR1_TMOD_Pos (9U) +#define DDRPHYC_DTPR1_TMOD_Msk (0x3U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DTPR1_TMOD DDRPHYC_DTPR1_TMOD_Msk /*!< tMOD */ +#define DDRPHYC_DTPR1_TMOD_0 (0x1U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR1_TMOD_1 (0x2U << DDRPHYC_DTPR1_TMOD_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR1_TRTODT_Pos (11U) +#define DDRPHYC_DTPR1_TRTODT_Msk (0x1U << DDRPHYC_DTPR1_TRTODT_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR1_TRTODT DDRPHYC_DTPR1_TRTODT_Msk /*!< tRTODT */ +#define DDRPHYC_DTPR1_TRFC_Pos (16U) +#define DDRPHYC_DTPR1_TRFC_Msk (0xFFU << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTPR1_TRFC DDRPHYC_DTPR1_TRFC_Msk /*!< tRFC */ +#define DDRPHYC_DTPR1_TRFC_0 (0x1U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR1_TRFC_1 (0x2U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR1_TRFC_2 (0x4U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR1_TRFC_3 (0x8U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR1_TRFC_4 (0x10U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR1_TRFC_5 (0x20U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR1_TRFC_6 (0x40U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR1_TRFC_7 (0x80U << DDRPHYC_DTPR1_TRFC_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_Pos (24U) +#define DDRPHYC_DTPR1_TDQSCKMIN_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x07000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN DDRPHYC_DTPR1_TDQSCKMIN_Msk /*!< tDQSCKmin */ +#define DDRPHYC_DTPR1_TDQSCKMIN_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR1_TDQSCKMIN_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMIN_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_Pos (27U) +#define DDRPHYC_DTPR1_TDQSCKMAX_Msk (0x7U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x38000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX DDRPHYC_DTPR1_TDQSCKMAX_Msk /*!< tDQSCKmax */ +#define DDRPHYC_DTPR1_TDQSCKMAX_0 (0x1U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_1 (0x2U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTPR1_TDQSCKMAX_2 (0x4U << DDRPHYC_DTPR1_TDQSCKMAX_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DTPR2 register *****************/ +#define DDRPHYC_DTPR2_TXS_Pos (0U) +#define DDRPHYC_DTPR2_TXS_Msk (0x3FFU << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x000003FF */ +#define DDRPHYC_DTPR2_TXS DDRPHYC_DTPR2_TXS_Msk /*!< tXS */ +#define DDRPHYC_DTPR2_TXS_0 (0x1U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTPR2_TXS_1 (0x2U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTPR2_TXS_2 (0x4U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTPR2_TXS_3 (0x8U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTPR2_TXS_4 (0x10U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTPR2_TXS_5 (0x20U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTPR2_TXS_6 (0x40U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTPR2_TXS_7 (0x80U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTPR2_TXS_8 (0x100U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTPR2_TXS_9 (0x200U << DDRPHYC_DTPR2_TXS_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTPR2_TXP_Pos (10U) +#define DDRPHYC_DTPR2_TXP_Msk (0x1FU << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00007C00 */ +#define DDRPHYC_DTPR2_TXP DDRPHYC_DTPR2_TXP_Msk /*!< tXP */ +#define DDRPHYC_DTPR2_TXP_0 (0x1U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTPR2_TXP_1 (0x2U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTPR2_TXP_2 (0x4U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTPR2_TXP_3 (0x8U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTPR2_TXP_4 (0x10U << DDRPHYC_DTPR2_TXP_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTPR2_TCKE_Pos (15U) +#define DDRPHYC_DTPR2_TCKE_Msk (0xFU << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00078000 */ +#define DDRPHYC_DTPR2_TCKE DDRPHYC_DTPR2_TCKE_Msk /*!< tCKE */ +#define DDRPHYC_DTPR2_TCKE_0 (0x1U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTPR2_TCKE_1 (0x2U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTPR2_TCKE_2 (0x4U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTPR2_TCKE_3 (0x8U << DDRPHYC_DTPR2_TCKE_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTPR2_TDLLK_Pos (19U) +#define DDRPHYC_DTPR2_TDLLK_Msk (0x3FFU << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x1FF80000 */ +#define DDRPHYC_DTPR2_TDLLK DDRPHYC_DTPR2_TDLLK_Msk /*!< tDLLK */ +#define DDRPHYC_DTPR2_TDLLK_0 (0x1U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTPR2_TDLLK_1 (0x2U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTPR2_TDLLK_2 (0x4U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTPR2_TDLLK_3 (0x8U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTPR2_TDLLK_4 (0x10U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTPR2_TDLLK_5 (0x20U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTPR2_TDLLK_6 (0x40U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTPR2_TDLLK_7 (0x80U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTPR2_TDLLK_8 (0x100U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTPR2_TDLLK_9 (0x200U << DDRPHYC_DTPR2_TDLLK_Pos) /*!< 0x10000000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR0 register ***************/ +#define DDRPHYC_DDR3_MR0_BL_Pos (0U) +#define DDRPHYC_DDR3_MR0_BL_Msk (0x3U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR0_BL DDRPHYC_DDR3_MR0_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR0_BL_0 (0x1U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR0_BL_1 (0x2U << DDRPHYC_DDR3_MR0_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR0_CL0_Pos (2U) +#define DDRPHYC_DDR3_MR0_CL0_Msk (0x1U << DDRPHYC_DDR3_MR0_CL0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR0_CL0 DDRPHYC_DDR3_MR0_CL0_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_BT_Pos (3U) +#define DDRPHYC_DDR3_MR0_BT_Msk (0x1U << DDRPHYC_DDR3_MR0_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR0_BT DDRPHYC_DDR3_MR0_BT_Msk /*!< Burst type */ +#define DDRPHYC_DDR3_MR0_CL_Pos (4U) +#define DDRPHYC_DDR3_MR0_CL_Msk (0x7U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000070 */ +#define DDRPHYC_DDR3_MR0_CL DDRPHYC_DDR3_MR0_CL_Msk /*!< CAS latency */ +#define DDRPHYC_DDR3_MR0_CL_0 (0x1U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR0_CL_1 (0x2U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR0_CL_2 (0x4U << DDRPHYC_DDR3_MR0_CL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR0_TM_Pos (7U) +#define DDRPHYC_DDR3_MR0_TM_Msk (0x1U << DDRPHYC_DDR3_MR0_TM_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR0_TM DDRPHYC_DDR3_MR0_TM_Msk /*!< Operating mode */ +#define DDRPHYC_DDR3_MR0_DR_Pos (8U) +#define DDRPHYC_DDR3_MR0_DR_Msk (0x1U << DDRPHYC_DDR3_MR0_DR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DDR3_MR0_DR DDRPHYC_DDR3_MR0_DR_Msk /*!< DLL reset (autoclear) */ +#define DDRPHYC_DDR3_MR0_WR_Pos (9U) +#define DDRPHYC_DDR3_MR0_WR_Msk (0x7U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DDR3_MR0_WR DDRPHYC_DDR3_MR0_WR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR0_WR_0 (0x1U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR0_WR_1 (0x2U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR0_WR_2 (0x4U << DDRPHYC_DDR3_MR0_WR_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR0_PD_Pos (12U) +#define DDRPHYC_DDR3_MR0_PD_Msk (0x1U << DDRPHYC_DDR3_MR0_PD_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR0_PD DDRPHYC_DDR3_MR0_PD_Msk /*!< Power-down control */ +#define DDRPHYC_DDR3_MR0_RSVD_Pos (13U) +#define DDRPHYC_DDR3_MR0_RSVD_Msk (0x7U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DDR3_MR0_RSVD DDRPHYC_DDR3_MR0_RSVD_Msk /*!< JEDEC reserved. */ +#define DDRPHYC_DDR3_MR0_RSVD_0 (0x1U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DDR3_MR0_RSVD_1 (0x2U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DDR3_MR0_RSVD_2 (0x4U << DDRPHYC_DDR3_MR0_RSVD_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR1 register ***************/ +#define DDRPHYC_DDR3_MR1_DE_Pos (0U) +#define DDRPHYC_DDR3_MR1_DE_Msk (0x1U << DDRPHYC_DDR3_MR1_DE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_DE DDRPHYC_DDR3_MR1_DE_Msk /*!< DLL enable/disable */ +#define DDRPHYC_DDR3_MR1_DIC0_Pos (1U) +#define DDRPHYC_DDR3_MR1_DIC0_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_DIC0 DDRPHYC_DDR3_MR1_DIC0_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT0_Pos (2U) +#define DDRPHYC_DDR3_MR1_RTT0_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_RTT0 DDRPHYC_DDR3_MR1_RTT0_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_AL_Pos (3U) +#define DDRPHYC_DDR3_MR1_AL_Msk (0x3U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000018 */ +#define DDRPHYC_DDR3_MR1_AL DDRPHYC_DDR3_MR1_AL_Msk /*!< Posted CAS Additive Latency: */ +#define DDRPHYC_DDR3_MR1_AL_0 (0x1U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_AL_1 (0x2U << DDRPHYC_DDR3_MR1_AL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_DIC1_Pos (5U) +#define DDRPHYC_DDR3_MR1_DIC1_Msk (0x1U << DDRPHYC_DDR3_MR1_DIC1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_DIC1 DDRPHYC_DDR3_MR1_DIC1_Msk /*!< Output driver impedance control */ +#define DDRPHYC_DDR3_MR1_RTT1_Pos (6U) +#define DDRPHYC_DDR3_MR1_RTT1_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_RTT1 DDRPHYC_DDR3_MR1_RTT1_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_LEVEL_Pos (7U) +#define DDRPHYC_DDR3_MR1_LEVEL_Msk (0x1U << DDRPHYC_DDR3_MR1_LEVEL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_LEVEL DDRPHYC_DDR3_MR1_LEVEL_Msk /*!< Write leveling enable (N/A) */ +#define DDRPHYC_DDR3_MR1_RTT2_Pos (9U) +#define DDRPHYC_DDR3_MR1_RTT2_Msk (0x1U << DDRPHYC_DDR3_MR1_RTT2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR1_RTT2 DDRPHYC_DDR3_MR1_RTT2_Msk /*!< On die termination */ +#define DDRPHYC_DDR3_MR1_TDQS_Pos (11U) +#define DDRPHYC_DDR3_MR1_TDQS_Msk (0x1U << DDRPHYC_DDR3_MR1_TDQS_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DDR3_MR1_TDQS DDRPHYC_DDR3_MR1_TDQS_Msk /*!< Termination data strobe */ +#define DDRPHYC_DDR3_MR1_QOFF_Pos (12U) +#define DDRPHYC_DDR3_MR1_QOFF_Msk (0x1U << DDRPHYC_DDR3_MR1_QOFF_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DDR3_MR1_QOFF DDRPHYC_DDR3_MR1_QOFF_Msk /*!< Output enable/disable */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_BT_Pos (3U) +#define DDRPHYC_DDR3_MR1_BT_Msk (0x1U << DDRPHYC_DDR3_MR1_BT_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR1_BT DDRPHYC_DDR3_MR1_BT_Msk /*!< Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). , */ +#define DDRPHYC_DDR3_MR1_WC_Pos (4U) +#define DDRPHYC_DDR3_MR1_WC_Msk (0x1U << DDRPHYC_DDR3_MR1_WC_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR1_WC DDRPHYC_DDR3_MR1_WC_Msk /*!< Wrap control */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR1_BL_Pos (0U) +#define DDRPHYC_DDR3_MR1_BL_Msk (0x7U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR1_BL DDRPHYC_DDR3_MR1_BL_Msk /*!< Burst length */ +#define DDRPHYC_DDR3_MR1_BL_0 (0x1U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR1_BL_1 (0x2U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR1_BL_2 (0x4U << DDRPHYC_DDR3_MR1_BL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR1_NWR_Pos (5U) +#define DDRPHYC_DDR3_MR1_NWR_Msk (0x7U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x000000E0 */ +#define DDRPHYC_DDR3_MR1_NWR DDRPHYC_DDR3_MR1_NWR_Msk /*!< Write recovery */ +#define DDRPHYC_DDR3_MR1_NWR_0 (0x1U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR1_NWR_1 (0x2U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR1_NWR_2 (0x4U << DDRPHYC_DDR3_MR1_NWR_Pos) /*!< 0x00000080 */ + +/*************** Bit definition for DDRPHYC_DDR3_MR2 register ***************/ +#define DDRPHYC_DDR3_MR2_PASR_Pos (0U) +#define DDRPHYC_DDR3_MR2_PASR_Msk (0x7U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_PASR DDRPHYC_DDR3_MR2_PASR_Msk /*!< Partial array self-refresh */ +#define DDRPHYC_DDR3_MR2_PASR_0 (0x1U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_PASR_1 (0x2U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_PASR_2 (0x4U << DDRPHYC_DDR3_MR2_PASR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_CWL_Pos (3U) +#define DDRPHYC_DDR3_MR2_CWL_Msk (0x7U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DDR3_MR2_CWL DDRPHYC_DDR3_MR2_CWL_Msk /*!< CAS write latency */ +#define DDRPHYC_DDR3_MR2_CWL_0 (0x1U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DDR3_MR2_CWL_1 (0x2U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_CWL_2 (0x4U << DDRPHYC_DDR3_MR2_CWL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DDR3_MR2_ASR_Pos (6U) +#define DDRPHYC_DDR3_MR2_ASR_Msk (0x1U << DDRPHYC_DDR3_MR2_ASR_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_ASR DDRPHYC_DDR3_MR2_ASR_Msk /*!< Auto self-refresh */ +#define DDRPHYC_DDR3_MR2_SRT_Pos (7U) +#define DDRPHYC_DDR3_MR2_SRT_Msk (0x1U << DDRPHYC_DDR3_MR2_SRT_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_SRT DDRPHYC_DDR3_MR2_SRT_Msk /*!< Self-refresh temperature range */ +#define DDRPHYC_DDR3_MR2_RTTWR_Pos (9U) +#define DDRPHYC_DDR3_MR2_RTTWR_Msk (0x3U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000600 */ +#define DDRPHYC_DDR3_MR2_RTTWR DDRPHYC_DDR3_MR2_RTTWR_Msk /*!< Dynamic ODT */ +#define DDRPHYC_DDR3_MR2_RTTWR_0 (0x1U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DDR3_MR2_RTTWR_1 (0x2U << DDRPHYC_DDR3_MR2_RTTWR_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_RLWL_Pos (0U) +#define DDRPHYC_DDR3_MR2_RLWL_Msk (0x7U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DDR3_MR2_RLWL DDRPHYC_DDR3_MR2_RLWL_Msk /*!< Read and write latency */ +#define DDRPHYC_DDR3_MR2_RLWL_0 (0x1U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR2_RLWL_1 (0x2U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR2_RLWL_2 (0x4U << DDRPHYC_DDR3_MR2_RLWL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR2_NWRE_Pos (4U) +#define DDRPHYC_DDR3_MR2_NWRE_Msk (0x1U << DDRPHYC_DDR3_MR2_NWRE_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DDR3_MR2_NWRE DDRPHYC_DDR3_MR2_NWRE_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WL_Pos (6U) +#define DDRPHYC_DDR3_MR2_WL_Msk (0x1U << DDRPHYC_DDR3_MR2_WL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DDR3_MR2_WL DDRPHYC_DDR3_MR2_WL_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ +#define DDRPHYC_DDR3_MR2_WR_Pos (7U) +#define DDRPHYC_DDR3_MR2_WR_Msk (0x1U << DDRPHYC_DDR3_MR2_WR_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DDR3_MR2_WR DDRPHYC_DDR3_MR2_WR_Msk /*!< New for LPDDR3 (not used by this PHY, leave at zero) */ + +/*************** Bit definition for DDRPHYC_DDR3_MR3 register ***************/ +#define DDRPHYC_DDR3_MR3_MPRLOC_Pos (0U) +#define DDRPHYC_DDR3_MR3_MPRLOC_Msk (0x3U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000003 */ +#define DDRPHYC_DDR3_MR3_MPRLOC DDRPHYC_DDR3_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) location */ +#define DDRPHYC_DDR3_MR3_MPRLOC_0 (0x1U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DDR3_MR3_MPRLOC_1 (0x2U << DDRPHYC_DDR3_MR3_MPRLOC_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DDR3_MR3_MPR_Pos (2U) +#define DDRPHYC_DDR3_MR3_MPR_Msk (0x1U << DDRPHYC_DDR3_MR3_MPR_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DDR3_MR3_MPR DDRPHYC_DDR3_MR3_MPR_Msk /*!< Multi-purpose register enable */ + +/**************** Bit definition for DDRPHYC_ODTCR register *****************/ +#define DDRPHYC_ODTCR_RDODT_Pos (0U) +#define DDRPHYC_ODTCR_RDODT_Msk (0x1U << DDRPHYC_ODTCR_RDODT_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ODTCR_RDODT DDRPHYC_ODTCR_RDODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on read */ +#define DDRPHYC_ODTCR_WRODT_Pos (16U) +#define DDRPHYC_ODTCR_WRODT_Msk (0x1U << DDRPHYC_ODTCR_WRODT_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ODTCR_WRODT DDRPHYC_ODTCR_WRODT_Msk /*!< Specifies whether ODT should be enabled ('1') or disabled ('0') on write */ + +/***************** Bit definition for DDRPHYC_DTAR register *****************/ +#define DDRPHYC_DTAR_DTCOL_Pos (0U) +#define DDRPHYC_DTAR_DTCOL_Msk (0xFFFU << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000FFF */ +#define DDRPHYC_DTAR_DTCOL DDRPHYC_DTAR_DTCOL_Msk /*!< Data training column address: */ +#define DDRPHYC_DTAR_DTCOL_0 (0x1U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTAR_DTCOL_1 (0x2U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTAR_DTCOL_2 (0x4U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTAR_DTCOL_3 (0x8U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTAR_DTCOL_4 (0x10U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTAR_DTCOL_5 (0x20U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTAR_DTCOL_6 (0x40U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTAR_DTCOL_7 (0x80U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTAR_DTCOL_8 (0x100U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTAR_DTCOL_9 (0x200U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTAR_DTCOL_10 (0x400U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTAR_DTCOL_11 (0x800U << DDRPHYC_DTAR_DTCOL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTAR_DTROW_Pos (12U) +#define DDRPHYC_DTAR_DTROW_Msk (0xFFFFU << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x0FFFF000 */ +#define DDRPHYC_DTAR_DTROW DDRPHYC_DTAR_DTROW_Msk /*!< Data training row address: */ +#define DDRPHYC_DTAR_DTROW_0 (0x1U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTAR_DTROW_1 (0x2U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTAR_DTROW_2 (0x4U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTAR_DTROW_3 (0x8U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTAR_DTROW_4 (0x10U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTAR_DTROW_5 (0x20U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTAR_DTROW_6 (0x40U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTAR_DTROW_7 (0x80U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTAR_DTROW_8 (0x100U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTAR_DTROW_9 (0x200U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTAR_DTROW_10 (0x400U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTAR_DTROW_11 (0x800U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTAR_DTROW_12 (0x1000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTAR_DTROW_13 (0x2000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTAR_DTROW_14 (0x4000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTAR_DTROW_15 (0x8000U << DDRPHYC_DTAR_DTROW_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTAR_DTBANK_Pos (28U) +#define DDRPHYC_DTAR_DTBANK_Msk (0x7U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x70000000 */ +#define DDRPHYC_DTAR_DTBANK DDRPHYC_DTAR_DTBANK_Msk /*!< Data training bank address: */ +#define DDRPHYC_DTAR_DTBANK_0 (0x1U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTAR_DTBANK_1 (0x2U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTAR_DTBANK_2 (0x4U << DDRPHYC_DTAR_DTBANK_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTAR_DTMPR_Pos (31U) +#define DDRPHYC_DTAR_DTMPR_Msk (0x1U << DDRPHYC_DTAR_DTMPR_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DTAR_DTMPR DDRPHYC_DTAR_DTMPR_Msk /*!< Data training using MPR (DDR3 Only): */ + +/**************** Bit definition for DDRPHYC_DTDR0 register *****************/ +#define DDRPHYC_DTDR0_DTBYTE0_Pos (0U) +#define DDRPHYC_DTDR0_DTBYTE0_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR0_DTBYTE0 DDRPHYC_DTDR0_DTBYTE0_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE0_0 (0x1U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR0_DTBYTE0_1 (0x2U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR0_DTBYTE0_2 (0x4U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR0_DTBYTE0_3 (0x8U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR0_DTBYTE0_4 (0x10U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR0_DTBYTE0_5 (0x20U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR0_DTBYTE0_6 (0x40U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR0_DTBYTE0_7 (0x80U << DDRPHYC_DTDR0_DTBYTE0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR0_DTBYTE1_Pos (8U) +#define DDRPHYC_DTDR0_DTBYTE1_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR0_DTBYTE1 DDRPHYC_DTDR0_DTBYTE1_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE1_0 (0x1U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR0_DTBYTE1_1 (0x2U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR0_DTBYTE1_2 (0x4U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR0_DTBYTE1_3 (0x8U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR0_DTBYTE1_4 (0x10U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR0_DTBYTE1_5 (0x20U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR0_DTBYTE1_6 (0x40U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR0_DTBYTE1_7 (0x80U << DDRPHYC_DTDR0_DTBYTE1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR0_DTBYTE2_Pos (16U) +#define DDRPHYC_DTDR0_DTBYTE2_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR0_DTBYTE2 DDRPHYC_DTDR0_DTBYTE2_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR0_DTBYTE2_0 (0x1U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR0_DTBYTE2_1 (0x2U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR0_DTBYTE2_2 (0x4U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR0_DTBYTE2_3 (0x8U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR0_DTBYTE2_4 (0x10U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR0_DTBYTE2_5 (0x20U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR0_DTBYTE2_6 (0x40U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR0_DTBYTE2_7 (0x80U << DDRPHYC_DTDR0_DTBYTE2_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR0_DTBYTE3_Pos (24U) +#define DDRPHYC_DTDR0_DTBYTE3_Msk (0xFFU << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR0_DTBYTE3 DDRPHYC_DTDR0_DTBYTE3_Msk /*!< Data training data */ +#define DDRPHYC_DTDR0_DTBYTE3_0 (0x1U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_1 (0x2U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_2 (0x4U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_3 (0x8U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_4 (0x10U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_5 (0x20U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_6 (0x40U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR0_DTBYTE3_7 (0x80U << DDRPHYC_DTDR0_DTBYTE3_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_DTDR1 register *****************/ +#define DDRPHYC_DTDR1_DTBYTE4_Pos (0U) +#define DDRPHYC_DTDR1_DTBYTE4_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x000000FF */ +#define DDRPHYC_DTDR1_DTBYTE4 DDRPHYC_DTDR1_DTBYTE4_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE4_0 (0x1U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DTDR1_DTBYTE4_1 (0x2U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DTDR1_DTBYTE4_2 (0x4U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DTDR1_DTBYTE4_3 (0x8U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DTDR1_DTBYTE4_4 (0x10U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DTDR1_DTBYTE4_5 (0x20U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DTDR1_DTBYTE4_6 (0x40U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DTDR1_DTBYTE4_7 (0x80U << DDRPHYC_DTDR1_DTBYTE4_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DTDR1_DTBYTE5_Pos (8U) +#define DDRPHYC_DTDR1_DTBYTE5_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x0000FF00 */ +#define DDRPHYC_DTDR1_DTBYTE5 DDRPHYC_DTDR1_DTBYTE5_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE5_0 (0x1U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DTDR1_DTBYTE5_1 (0x2U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DTDR1_DTBYTE5_2 (0x4U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DTDR1_DTBYTE5_3 (0x8U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DTDR1_DTBYTE5_4 (0x10U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DTDR1_DTBYTE5_5 (0x20U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DTDR1_DTBYTE5_6 (0x40U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DTDR1_DTBYTE5_7 (0x80U << DDRPHYC_DTDR1_DTBYTE5_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DTDR1_DTBYTE6_Pos (16U) +#define DDRPHYC_DTDR1_DTBYTE6_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00FF0000 */ +#define DDRPHYC_DTDR1_DTBYTE6 DDRPHYC_DTDR1_DTBYTE6_Msk /*!< Data Training Data */ +#define DDRPHYC_DTDR1_DTBYTE6_0 (0x1U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DTDR1_DTBYTE6_1 (0x2U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DTDR1_DTBYTE6_2 (0x4U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DTDR1_DTBYTE6_3 (0x8U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DTDR1_DTBYTE6_4 (0x10U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DTDR1_DTBYTE6_5 (0x20U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DTDR1_DTBYTE6_6 (0x40U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DTDR1_DTBYTE6_7 (0x80U << DDRPHYC_DTDR1_DTBYTE6_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DTDR1_DTBYTE7_Pos (24U) +#define DDRPHYC_DTDR1_DTBYTE7_Msk (0xFFU << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0xFF000000 */ +#define DDRPHYC_DTDR1_DTBYTE7 DDRPHYC_DTDR1_DTBYTE7_Msk /*!< Data training data: */ +#define DDRPHYC_DTDR1_DTBYTE7_0 (0x1U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_1 (0x2U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_2 (0x4U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_3 (0x8U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_4 (0x10U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_5 (0x20U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_6 (0x40U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DTDR1_DTBYTE7_7 (0x80U << DDRPHYC_DTDR1_DTBYTE7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR0 register *****************/ +#define DDRPHYC_GPR0_GPR0_Pos (0U) +#define DDRPHYC_GPR0_GPR0_Msk (0xFFFFFFFFU << DDRPHYC_GPR0_GPR0_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR0_GPR0 DDRPHYC_GPR0_GPR0_Msk /*!< General purpose register 0 bits */ +#define DDRPHYC_GPR0_GPR0_0 (0x1U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR0_GPR0_1 (0x2U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR0_GPR0_2 (0x4U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR0_GPR0_3 (0x8U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR0_GPR0_4 (0x10U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR0_GPR0_5 (0x20U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR0_GPR0_6 (0x40U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR0_GPR0_7 (0x80U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR0_GPR0_8 (0x100U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR0_GPR0_9 (0x200U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR0_GPR0_10 (0x400U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR0_GPR0_11 (0x800U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR0_GPR0_12 (0x1000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR0_GPR0_13 (0x2000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR0_GPR0_14 (0x4000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR0_GPR0_15 (0x8000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR0_GPR0_16 (0x10000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR0_GPR0_17 (0x20000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR0_GPR0_18 (0x40000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR0_GPR0_19 (0x80000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR0_GPR0_20 (0x100000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR0_GPR0_21 (0x200000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR0_GPR0_22 (0x400000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR0_GPR0_23 (0x800000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR0_GPR0_24 (0x1000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR0_GPR0_25 (0x2000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR0_GPR0_26 (0x4000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR0_GPR0_27 (0x8000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR0_GPR0_28 (0x10000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR0_GPR0_29 (0x20000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR0_GPR0_30 (0x40000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR0_GPR0_31 (0x80000000U << DDRPHYC_GPR0_GPR0_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for DDRPHYC_GPR1 register *****************/ +#define DDRPHYC_GPR1_GPR1_Pos (0U) +#define DDRPHYC_GPR1_GPR1_Msk (0xFFFFFFFFU << DDRPHYC_GPR1_GPR1_Pos) /*!< 0xFFFFFFFF */ +#define DDRPHYC_GPR1_GPR1 DDRPHYC_GPR1_GPR1_Msk /*!< General purpose register 1 bits */ +#define DDRPHYC_GPR1_GPR1_0 (0x1U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000001 */ +#define DDRPHYC_GPR1_GPR1_1 (0x2U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000002 */ +#define DDRPHYC_GPR1_GPR1_2 (0x4U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000004 */ +#define DDRPHYC_GPR1_GPR1_3 (0x8U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000008 */ +#define DDRPHYC_GPR1_GPR1_4 (0x10U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_GPR1_GPR1_5 (0x20U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_GPR1_GPR1_6 (0x40U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_GPR1_GPR1_7 (0x80U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_GPR1_GPR1_8 (0x100U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000100 */ +#define DDRPHYC_GPR1_GPR1_9 (0x200U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000200 */ +#define DDRPHYC_GPR1_GPR1_10 (0x400U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000400 */ +#define DDRPHYC_GPR1_GPR1_11 (0x800U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00000800 */ +#define DDRPHYC_GPR1_GPR1_12 (0x1000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00001000 */ +#define DDRPHYC_GPR1_GPR1_13 (0x2000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00002000 */ +#define DDRPHYC_GPR1_GPR1_14 (0x4000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00004000 */ +#define DDRPHYC_GPR1_GPR1_15 (0x8000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00008000 */ +#define DDRPHYC_GPR1_GPR1_16 (0x10000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00010000 */ +#define DDRPHYC_GPR1_GPR1_17 (0x20000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00020000 */ +#define DDRPHYC_GPR1_GPR1_18 (0x40000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00040000 */ +#define DDRPHYC_GPR1_GPR1_19 (0x80000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00080000 */ +#define DDRPHYC_GPR1_GPR1_20 (0x100000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00100000 */ +#define DDRPHYC_GPR1_GPR1_21 (0x200000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00200000 */ +#define DDRPHYC_GPR1_GPR1_22 (0x400000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00400000 */ +#define DDRPHYC_GPR1_GPR1_23 (0x800000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x00800000 */ +#define DDRPHYC_GPR1_GPR1_24 (0x1000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x01000000 */ +#define DDRPHYC_GPR1_GPR1_25 (0x2000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x02000000 */ +#define DDRPHYC_GPR1_GPR1_26 (0x4000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x04000000 */ +#define DDRPHYC_GPR1_GPR1_27 (0x8000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x08000000 */ +#define DDRPHYC_GPR1_GPR1_28 (0x10000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x10000000 */ +#define DDRPHYC_GPR1_GPR1_29 (0x20000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x20000000 */ +#define DDRPHYC_GPR1_GPR1_30 (0x40000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x40000000 */ +#define DDRPHYC_GPR1_GPR1_31 (0x80000000U << DDRPHYC_GPR1_GPR1_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for DDRPHYC_ZQ0CR0 register ****************/ +#define DDRPHYC_ZQ0CR0_ZDATA_Pos (0U) +#define DDRPHYC_ZQ0CR0_ZDATA_Msk (0xFFFFFU << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0CR0_ZDATA DDRPHYC_ZQ0CR0_ZDATA_Msk /*!< Impedance override */ +#define DDRPHYC_ZQ0CR0_ZDATA_0 (0x1U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR0_ZDATA_1 (0x2U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR0_ZDATA_2 (0x4U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR0_ZDATA_3 (0x8U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR0_ZDATA_4 (0x10U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR0_ZDATA_5 (0x20U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR0_ZDATA_6 (0x40U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR0_ZDATA_7 (0x80U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0CR0_ZDATA_8 (0x100U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0CR0_ZDATA_9 (0x200U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0CR0_ZDATA_10 (0x400U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0CR0_ZDATA_11 (0x800U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0CR0_ZDATA_12 (0x1000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_13 (0x2000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_14 (0x4000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_15 (0x8000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_16 (0x10000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_17 (0x20000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_18 (0x40000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0CR0_ZDATA_19 (0x80000U << DDRPHYC_ZQ0CR0_ZDATA_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0CR0_ZDEN_Pos (28U) +#define DDRPHYC_ZQ0CR0_ZDEN_Msk (0x1U << DDRPHYC_ZQ0CR0_ZDEN_Pos) /*!< 0x10000000 */ +#define DDRPHYC_ZQ0CR0_ZDEN DDRPHYC_ZQ0CR0_ZDEN_Msk /*!< Impedance override enable */ +#define DDRPHYC_ZQ0CR0_ZCALBYP_Pos (29U) +#define DDRPHYC_ZQ0CR0_ZCALBYP_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCALBYP_Pos) /*!< 0x20000000 */ +#define DDRPHYC_ZQ0CR0_ZCALBYP DDRPHYC_ZQ0CR0_ZCALBYP_Msk /*!< Impedance calibration bypass */ +#define DDRPHYC_ZQ0CR0_ZCAL_Pos (30U) +#define DDRPHYC_ZQ0CR0_ZCAL_Msk (0x1U << DDRPHYC_ZQ0CR0_ZCAL_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0CR0_ZCAL DDRPHYC_ZQ0CR0_ZCAL_Msk /*!< ZCAL trigger */ +#define DDRPHYC_ZQ0CR0_ZQPD_Pos (31U) +#define DDRPHYC_ZQ0CR0_ZQPD_Msk (0x1U << DDRPHYC_ZQ0CR0_ZQPD_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0CR0_ZQPD DDRPHYC_ZQ0CR0_ZQPD_Msk /*!< ZCAL power down */ + +/**************** Bit definition for DDRPHYC_ZQ0CR1 register ****************/ +#define DDRPHYC_ZQ0CR1_ZPROG_Pos (0U) +#define DDRPHYC_ZQ0CR1_ZPROG_Msk (0xFFU << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x000000FF */ +#define DDRPHYC_ZQ0CR1_ZPROG DDRPHYC_ZQ0CR1_ZPROG_Msk /*!< Impedance divide ratio to ext R */ +#define DDRPHYC_ZQ0CR1_ZPROG_0 (0x1U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0CR1_ZPROG_1 (0x2U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0CR1_ZPROG_2 (0x4U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0CR1_ZPROG_3 (0x8U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0CR1_ZPROG_4 (0x10U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0CR1_ZPROG_5 (0x20U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0CR1_ZPROG_6 (0x40U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0CR1_ZPROG_7 (0x80U << DDRPHYC_ZQ0CR1_ZPROG_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_ZQ0SR0 register ****************/ +#define DDRPHYC_ZQ0SR0_ZCTRL_Pos (0U) +#define DDRPHYC_ZQ0SR0_ZCTRL_Msk (0xFFFFFU << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x000FFFFF */ +#define DDRPHYC_ZQ0SR0_ZCTRL DDRPHYC_ZQ0SR0_ZCTRL_Msk /*!< Impedance control */ +#define DDRPHYC_ZQ0SR0_ZCTRL_0 (0x1U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_1 (0x2U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_2 (0x4U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_3 (0x8U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_4 (0x10U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_5 (0x20U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_6 (0x40U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_7 (0x80U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000080 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_8 (0x100U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000100 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_9 (0x200U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000200 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_10 (0x400U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000400 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_11 (0x800U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00000800 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_12 (0x1000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00001000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_13 (0x2000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_14 (0x4000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_15 (0x8000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_16 (0x10000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00010000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_17 (0x20000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00020000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_18 (0x40000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00040000 */ +#define DDRPHYC_ZQ0SR0_ZCTRL_19 (0x80000U << DDRPHYC_ZQ0SR0_ZCTRL_Pos) /*!< 0x00080000 */ +#define DDRPHYC_ZQ0SR0_ZERR_Pos (30U) +#define DDRPHYC_ZQ0SR0_ZERR_Msk (0x1U << DDRPHYC_ZQ0SR0_ZERR_Pos) /*!< 0x40000000 */ +#define DDRPHYC_ZQ0SR0_ZERR DDRPHYC_ZQ0SR0_ZERR_Msk /*!< Impedance calibration error */ +#define DDRPHYC_ZQ0SR0_ZDONE_Pos (31U) +#define DDRPHYC_ZQ0SR0_ZDONE_Msk (0x1U << DDRPHYC_ZQ0SR0_ZDONE_Pos) /*!< 0x80000000 */ +#define DDRPHYC_ZQ0SR0_ZDONE DDRPHYC_ZQ0SR0_ZDONE_Msk /*!< Impedance calibration done */ + +/**************** Bit definition for DDRPHYC_ZQ0SR1 register ****************/ +#define DDRPHYC_ZQ0SR1_ZPD_Pos (0U) +#define DDRPHYC_ZQ0SR1_ZPD_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000003 */ +#define DDRPHYC_ZQ0SR1_ZPD DDRPHYC_ZQ0SR1_ZPD_Msk /*!< zpd calibration status */ +#define DDRPHYC_ZQ0SR1_ZPD_0 (0x1U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000001 */ +#define DDRPHYC_ZQ0SR1_ZPD_1 (0x2U << DDRPHYC_ZQ0SR1_ZPD_Pos) /*!< 0x00000002 */ +#define DDRPHYC_ZQ0SR1_ZPU_Pos (2U) +#define DDRPHYC_ZQ0SR1_ZPU_Msk (0x3U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x0000000C */ +#define DDRPHYC_ZQ0SR1_ZPU DDRPHYC_ZQ0SR1_ZPU_Msk /*!< zpu calibration status */ +#define DDRPHYC_ZQ0SR1_ZPU_0 (0x1U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000004 */ +#define DDRPHYC_ZQ0SR1_ZPU_1 (0x2U << DDRPHYC_ZQ0SR1_ZPU_Pos) /*!< 0x00000008 */ +#define DDRPHYC_ZQ0SR1_OPD_Pos (4U) +#define DDRPHYC_ZQ0SR1_OPD_Msk (0x3U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000030 */ +#define DDRPHYC_ZQ0SR1_OPD DDRPHYC_ZQ0SR1_OPD_Msk /*!< opd calibration status */ +#define DDRPHYC_ZQ0SR1_OPD_0 (0x1U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_ZQ0SR1_OPD_1 (0x2U << DDRPHYC_ZQ0SR1_OPD_Pos) /*!< 0x00000020 */ +#define DDRPHYC_ZQ0SR1_OPU_Pos (6U) +#define DDRPHYC_ZQ0SR1_OPU_Msk (0x3U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x000000C0 */ +#define DDRPHYC_ZQ0SR1_OPU DDRPHYC_ZQ0SR1_OPU_Msk /*!< opu calibration status */ +#define DDRPHYC_ZQ0SR1_OPU_0 (0x1U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000040 */ +#define DDRPHYC_ZQ0SR1_OPU_1 (0x2U << DDRPHYC_ZQ0SR1_OPU_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for DDRPHYC_DX0GCR register ****************/ +#define DDRPHYC_DX0GCR_DXEN_Pos (0U) +#define DDRPHYC_DX0GCR_DXEN_Msk (0x1U << DDRPHYC_DX0GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GCR_DXEN DDRPHYC_DX0GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX0GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX0GCR_DQSODT_Msk (0x1U << DDRPHYC_DX0GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0GCR_DQSODT DDRPHYC_DX0GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX0GCR_DQODT_Pos (2U) +#define DDRPHYC_DX0GCR_DQODT_Msk (0x1U << DDRPHYC_DX0GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0GCR_DQODT DDRPHYC_DX0GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX0GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX0GCR_DXIOM_Msk (0x1U << DDRPHYC_DX0GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0GCR_DXIOM DDRPHYC_DX0GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX0GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX0GCR_DXPDD_Msk (0x1U << DDRPHYC_DX0GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX0GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX0GCR_DXPDR_Msk (0x1U << DDRPHYC_DX0GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX0GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX0GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX0GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX0GCR_DSEN_Pos (7U) +#define DDRPHYC_DX0GCR_DSEN_Msk (0x3U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX0GCR_DSEN DDRPHYC_DX0GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX0GCR_DSEN_0 (0x1U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0GCR_DSEN_1 (0x2U << DDRPHYC_DX0GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX0GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0GCR_DQSRTT DDRPHYC_DX0GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX0GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX0GCR_DQRTT_Msk (0x1U << DDRPHYC_DX0GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0GCR_DQRTT DDRPHYC_DX0GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX0GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX0GCR_RTTOH_Msk (0x3U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX0GCR_RTTOH DDRPHYC_DX0GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX0GCR_RTTOH_0 (0x1U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0GCR_RTTOH_1 (0x2U << DDRPHYC_DX0GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX0GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX0GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GCR_RTTOAL DDRPHYC_DX0GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX0GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX0GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX0GCR_R0RVSL DDRPHYC_DX0GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX0GCR_R0RVSL_0 (0x1U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GCR_R0RVSL_1 (0x2U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0GCR_R0RVSL_2 (0x4U << DDRPHYC_DX0GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR0 register ****************/ +#define DDRPHYC_DX0GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX0GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX0GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR0_DTDONE DDRPHYC_DX0GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX0GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX0GSR0_DTERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR0_DTERR DDRPHYC_DX0GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX0GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX0GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX0GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0GSR0_DTIERR DDRPHYC_DX0GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX0GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX0GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX0GSR0_DTPASS DDRPHYC_DX0GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX0GSR0_DTPASS_0 (0x1U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0GSR0_DTPASS_1 (0x2U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0GSR0_DTPASS_2 (0x4U << DDRPHYC_DX0GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX0GSR1 register ****************/ +#define DDRPHYC_DX0GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX0GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX0GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0GSR1_DFTERR DDRPHYC_DX0GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX0GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX0GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX0GSR1_DQSDFT DDRPHYC_DX0GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX0GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX0GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX0GSR1_RVERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0GSR1_RVERR DDRPHYC_DX0GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX0GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX0GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX0GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0GSR1_RVIERR DDRPHYC_DX0GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX0GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX0GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0GSR1_RVPASS DDRPHYC_DX0GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX0GSR1_RVPASS_0 (0x1U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0GSR1_RVPASS_1 (0x2U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0GSR1_RVPASS_2 (0x4U << DDRPHYC_DX0GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX0DLLCR register ***************/ +#define DDRPHYC_DX0DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX0DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX0DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX0DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX0DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX0DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX0DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX0DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX0DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DLLCR_SSTART DDRPHYC_DX0DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX0DLLCR_SSTART_0 (0x1U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DLLCR_SSTART_1 (0x2U << DDRPHYC_DX0DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX0DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE DDRPHYC_DX0DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX0DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX0DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX0DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX0DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DLLCR_ATESTEN DDRPHYC_DX0DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX0DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX0DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX0DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DLLCR_SDLBMODE DDRPHYC_DX0DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX0DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX0DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DLLCR_DLLSRST DDRPHYC_DX0DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX0DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX0DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX0DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX0DLLCR_DLLDIS DDRPHYC_DX0DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX0DQTR register ****************/ +#define DDRPHYC_DX0DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX0DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX0DQTR_DQDLY0 DDRPHYC_DX0DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX0DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX0DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX0DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX0DQTR_DQDLY1 DDRPHYC_DX0DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX0DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX0DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX0DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX0DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX0DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX0DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX0DQTR_DQDLY2 DDRPHYC_DX0DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX0DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX0DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX0DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX0DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX0DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX0DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX0DQTR_DQDLY3 DDRPHYC_DX0DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX0DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX0DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX0DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX0DQTR_DQDLY4 DDRPHYC_DX0DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX0DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX0DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX0DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX0DQTR_DQDLY5 DDRPHYC_DX0DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX0DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX0DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6 DDRPHYC_DX0DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX0DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX0DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7 DDRPHYC_DX0DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX0DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX0DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX0DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX0DQSTR register ***************/ +#define DDRPHYC_DX0DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX0DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX0DQSTR_R0DGSL DDRPHYC_DX0DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX0DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX0DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX0DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX0DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS DDRPHYC_DX0DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX0DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX0DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX0DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX0DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY DDRPHYC_DX0DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX0DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX0DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX0DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY DDRPHYC_DX0DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX0DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX0DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY DDRPHYC_DX0DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX0DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX0DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX0DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX1GCR register ****************/ +#define DDRPHYC_DX1GCR_DXEN_Pos (0U) +#define DDRPHYC_DX1GCR_DXEN_Msk (0x1U << DDRPHYC_DX1GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GCR_DXEN DDRPHYC_DX1GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX1GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX1GCR_DQSODT_Msk (0x1U << DDRPHYC_DX1GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1GCR_DQSODT DDRPHYC_DX1GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX1GCR_DQODT_Pos (2U) +#define DDRPHYC_DX1GCR_DQODT_Msk (0x1U << DDRPHYC_DX1GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1GCR_DQODT DDRPHYC_DX1GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX1GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX1GCR_DXIOM_Msk (0x1U << DDRPHYC_DX1GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1GCR_DXIOM DDRPHYC_DX1GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX1GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX1GCR_DXPDD_Msk (0x1U << DDRPHYC_DX1GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX1GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX1GCR_DXPDR_Msk (0x1U << DDRPHYC_DX1GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX1GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX1GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX1GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX1GCR_DSEN_Pos (7U) +#define DDRPHYC_DX1GCR_DSEN_Msk (0x3U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX1GCR_DSEN DDRPHYC_DX1GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX1GCR_DSEN_0 (0x1U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1GCR_DSEN_1 (0x2U << DDRPHYC_DX1GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX1GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1GCR_DQSRTT DDRPHYC_DX1GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX1GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX1GCR_DQRTT_Msk (0x1U << DDRPHYC_DX1GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1GCR_DQRTT DDRPHYC_DX1GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX1GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX1GCR_RTTOH_Msk (0x3U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX1GCR_RTTOH DDRPHYC_DX1GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX1GCR_RTTOH_0 (0x1U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1GCR_RTTOH_1 (0x2U << DDRPHYC_DX1GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX1GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX1GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GCR_RTTOAL DDRPHYC_DX1GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX1GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX1GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX1GCR_R0RVSL DDRPHYC_DX1GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX1GCR_R0RVSL_0 (0x1U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GCR_R0RVSL_1 (0x2U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1GCR_R0RVSL_2 (0x4U << DDRPHYC_DX1GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR0 register ****************/ +#define DDRPHYC_DX1GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX1GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX1GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR0_DTDONE DDRPHYC_DX1GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX1GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX1GSR0_DTERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR0_DTERR DDRPHYC_DX1GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX1GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX1GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX1GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1GSR0_DTIERR DDRPHYC_DX1GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX1GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX1GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX1GSR0_DTPASS DDRPHYC_DX1GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX1GSR0_DTPASS_0 (0x1U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1GSR0_DTPASS_1 (0x2U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1GSR0_DTPASS_2 (0x4U << DDRPHYC_DX1GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX1GSR1 register ****************/ +#define DDRPHYC_DX1GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX1GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX1GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1GSR1_DFTERR DDRPHYC_DX1GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX1GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX1GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX1GSR1_DQSDFT DDRPHYC_DX1GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX1GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX1GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX1GSR1_RVERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1GSR1_RVERR DDRPHYC_DX1GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX1GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX1GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX1GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1GSR1_RVIERR DDRPHYC_DX1GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX1GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX1GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1GSR1_RVPASS DDRPHYC_DX1GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX1GSR1_RVPASS_0 (0x1U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1GSR1_RVPASS_1 (0x2U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1GSR1_RVPASS_2 (0x4U << DDRPHYC_DX1GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX1DLLCR register ***************/ +#define DDRPHYC_DX1DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX1DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX1DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX1DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX1DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX1DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX1DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX1DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX1DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DLLCR_SSTART DDRPHYC_DX1DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX1DLLCR_SSTART_0 (0x1U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DLLCR_SSTART_1 (0x2U << DDRPHYC_DX1DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX1DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE DDRPHYC_DX1DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX1DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX1DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX1DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX1DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DLLCR_ATESTEN DDRPHYC_DX1DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX1DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX1DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX1DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DLLCR_SDLBMODE DDRPHYC_DX1DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX1DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX1DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DLLCR_DLLSRST DDRPHYC_DX1DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX1DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX1DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX1DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX1DLLCR_DLLDIS DDRPHYC_DX1DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX1DQTR register ****************/ +#define DDRPHYC_DX1DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX1DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX1DQTR_DQDLY0 DDRPHYC_DX1DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX1DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX1DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX1DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX1DQTR_DQDLY1 DDRPHYC_DX1DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX1DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX1DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX1DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX1DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX1DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX1DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX1DQTR_DQDLY2 DDRPHYC_DX1DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX1DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX1DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX1DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX1DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX1DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX1DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX1DQTR_DQDLY3 DDRPHYC_DX1DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX1DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX1DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX1DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX1DQTR_DQDLY4 DDRPHYC_DX1DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX1DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX1DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX1DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX1DQTR_DQDLY5 DDRPHYC_DX1DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX1DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX1DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6 DDRPHYC_DX1DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX1DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX1DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7 DDRPHYC_DX1DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX1DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX1DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX1DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX1DQSTR register ***************/ +#define DDRPHYC_DX1DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX1DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX1DQSTR_R0DGSL DDRPHYC_DX1DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX1DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX1DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX1DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX1DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS DDRPHYC_DX1DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX1DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX1DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX1DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX1DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY DDRPHYC_DX1DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX1DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX1DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX1DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY DDRPHYC_DX1DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX1DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX1DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY DDRPHYC_DX1DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX1DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX1DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX1DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX2GCR register ****************/ +#define DDRPHYC_DX2GCR_DXEN_Pos (0U) +#define DDRPHYC_DX2GCR_DXEN_Msk (0x1U << DDRPHYC_DX2GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GCR_DXEN DDRPHYC_DX2GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX2GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX2GCR_DQSODT_Msk (0x1U << DDRPHYC_DX2GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2GCR_DQSODT DDRPHYC_DX2GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX2GCR_DQODT_Pos (2U) +#define DDRPHYC_DX2GCR_DQODT_Msk (0x1U << DDRPHYC_DX2GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2GCR_DQODT DDRPHYC_DX2GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX2GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX2GCR_DXIOM_Msk (0x1U << DDRPHYC_DX2GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2GCR_DXIOM DDRPHYC_DX2GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX2GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX2GCR_DXPDD_Msk (0x1U << DDRPHYC_DX2GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX2GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX2GCR_DXPDR_Msk (0x1U << DDRPHYC_DX2GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX2GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX2GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX2GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX2GCR_DSEN_Pos (7U) +#define DDRPHYC_DX2GCR_DSEN_Msk (0x3U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX2GCR_DSEN DDRPHYC_DX2GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX2GCR_DSEN_0 (0x1U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2GCR_DSEN_1 (0x2U << DDRPHYC_DX2GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX2GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2GCR_DQSRTT DDRPHYC_DX2GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX2GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX2GCR_DQRTT_Msk (0x1U << DDRPHYC_DX2GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2GCR_DQRTT DDRPHYC_DX2GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX2GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX2GCR_RTTOH_Msk (0x3U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX2GCR_RTTOH DDRPHYC_DX2GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX2GCR_RTTOH_0 (0x1U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2GCR_RTTOH_1 (0x2U << DDRPHYC_DX2GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX2GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX2GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GCR_RTTOAL DDRPHYC_DX2GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX2GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX2GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX2GCR_R0RVSL DDRPHYC_DX2GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX2GCR_R0RVSL_0 (0x1U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GCR_R0RVSL_1 (0x2U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2GCR_R0RVSL_2 (0x4U << DDRPHYC_DX2GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR0 register ****************/ +#define DDRPHYC_DX2GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX2GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX2GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR0_DTDONE DDRPHYC_DX2GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX2GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX2GSR0_DTERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR0_DTERR DDRPHYC_DX2GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX2GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX2GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX2GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2GSR0_DTIERR DDRPHYC_DX2GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX2GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX2GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX2GSR0_DTPASS DDRPHYC_DX2GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX2GSR0_DTPASS_0 (0x1U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2GSR0_DTPASS_1 (0x2U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2GSR0_DTPASS_2 (0x4U << DDRPHYC_DX2GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX2GSR1 register ****************/ +#define DDRPHYC_DX2GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX2GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX2GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2GSR1_DFTERR DDRPHYC_DX2GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX2GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX2GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX2GSR1_DQSDFT DDRPHYC_DX2GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX2GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX2GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX2GSR1_RVERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2GSR1_RVERR DDRPHYC_DX2GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX2GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX2GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX2GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2GSR1_RVIERR DDRPHYC_DX2GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX2GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX2GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2GSR1_RVPASS DDRPHYC_DX2GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX2GSR1_RVPASS_0 (0x1U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2GSR1_RVPASS_1 (0x2U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2GSR1_RVPASS_2 (0x4U << DDRPHYC_DX2GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX2DLLCR register ***************/ +#define DDRPHYC_DX2DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX2DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX2DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX2DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX2DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX2DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX2DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX2DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX2DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DLLCR_SSTART DDRPHYC_DX2DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX2DLLCR_SSTART_0 (0x1U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DLLCR_SSTART_1 (0x2U << DDRPHYC_DX2DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX2DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE DDRPHYC_DX2DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX2DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX2DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX2DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX2DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DLLCR_ATESTEN DDRPHYC_DX2DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX2DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX2DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX2DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DLLCR_SDLBMODE DDRPHYC_DX2DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX2DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX2DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DLLCR_DLLSRST DDRPHYC_DX2DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX2DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX2DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX2DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX2DLLCR_DLLDIS DDRPHYC_DX2DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX2DQTR register ****************/ +#define DDRPHYC_DX2DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX2DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX2DQTR_DQDLY0 DDRPHYC_DX2DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX2DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX2DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX2DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX2DQTR_DQDLY1 DDRPHYC_DX2DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX2DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX2DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX2DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX2DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX2DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX2DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX2DQTR_DQDLY2 DDRPHYC_DX2DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX2DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX2DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX2DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX2DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX2DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX2DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX2DQTR_DQDLY3 DDRPHYC_DX2DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX2DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX2DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX2DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX2DQTR_DQDLY4 DDRPHYC_DX2DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX2DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX2DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX2DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX2DQTR_DQDLY5 DDRPHYC_DX2DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX2DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX2DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6 DDRPHYC_DX2DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX2DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX2DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7 DDRPHYC_DX2DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX2DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX2DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX2DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX2DQSTR register ***************/ +#define DDRPHYC_DX2DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX2DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX2DQSTR_R0DGSL DDRPHYC_DX2DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX2DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX2DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX2DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX2DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS DDRPHYC_DX2DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX2DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX2DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX2DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX2DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY DDRPHYC_DX2DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX2DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX2DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX2DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY DDRPHYC_DX2DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX2DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX2DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY DDRPHYC_DX2DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX2DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX2DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX2DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + +/**************** Bit definition for DDRPHYC_DX3GCR register ****************/ +#define DDRPHYC_DX3GCR_DXEN_Pos (0U) +#define DDRPHYC_DX3GCR_DXEN_Msk (0x1U << DDRPHYC_DX3GCR_DXEN_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GCR_DXEN DDRPHYC_DX3GCR_DXEN_Msk /*!< DATA byte enable */ +#define DDRPHYC_DX3GCR_DQSODT_Pos (1U) +#define DDRPHYC_DX3GCR_DQSODT_Msk (0x1U << DDRPHYC_DX3GCR_DQSODT_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3GCR_DQSODT DDRPHYC_DX3GCR_DQSODT_Msk /*!< DQS ODT enable */ +#define DDRPHYC_DX3GCR_DQODT_Pos (2U) +#define DDRPHYC_DX3GCR_DQODT_Msk (0x1U << DDRPHYC_DX3GCR_DQODT_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3GCR_DQODT DDRPHYC_DX3GCR_DQODT_Msk /*!< DQ ODT enable */ +#define DDRPHYC_DX3GCR_DXIOM_Pos (3U) +#define DDRPHYC_DX3GCR_DXIOM_Msk (0x1U << DDRPHYC_DX3GCR_DXIOM_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3GCR_DXIOM DDRPHYC_DX3GCR_DXIOM_Msk /*!< Data I/O mode */ +#define DDRPHYC_DX3GCR_DXPDD_Pos (4U) +#define DDRPHYC_DX3GCR_DXPDD_Msk (0x1U << DDRPHYC_DX3GCR_DXPDD_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */ +#define DDRPHYC_DX3GCR_DXPDR_Pos (5U) +#define DDRPHYC_DX3GCR_DXPDR_Msk (0x1U << DDRPHYC_DX3GCR_DXPDR_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver */ +#define DDRPHYC_DX3GCR_DQSRPD_Pos (6U) +#define DDRPHYC_DX3GCR_DQSRPD_Msk (0x1U << DDRPHYC_DX3GCR_DQSRPD_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */ +#define DDRPHYC_DX3GCR_DSEN_Pos (7U) +#define DDRPHYC_DX3GCR_DSEN_Msk (0x3U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000180 */ +#define DDRPHYC_DX3GCR_DSEN DDRPHYC_DX3GCR_DSEN_Msk /*!< Write DQS enable */ +#define DDRPHYC_DX3GCR_DSEN_0 (0x1U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3GCR_DSEN_1 (0x2U << DDRPHYC_DX3GCR_DSEN_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GCR_DQSRTT_Pos (9U) +#define DDRPHYC_DX3GCR_DQSRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQSRTT_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3GCR_DQSRTT DDRPHYC_DX3GCR_DQSRTT_Msk /*!< DQS dynamic RTT control */ +#define DDRPHYC_DX3GCR_DQRTT_Pos (10U) +#define DDRPHYC_DX3GCR_DQRTT_Msk (0x1U << DDRPHYC_DX3GCR_DQRTT_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3GCR_DQRTT DDRPHYC_DX3GCR_DQRTT_Msk /*!< DQ dynamic RTT control */ +#define DDRPHYC_DX3GCR_RTTOH_Pos (11U) +#define DDRPHYC_DX3GCR_RTTOH_Msk (0x3U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001800 */ +#define DDRPHYC_DX3GCR_RTTOH DDRPHYC_DX3GCR_RTTOH_Msk /*!< RTT output hold */ +#define DDRPHYC_DX3GCR_RTTOH_0 (0x1U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3GCR_RTTOH_1 (0x2U << DDRPHYC_DX3GCR_RTTOH_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GCR_RTTOAL_Pos (13U) +#define DDRPHYC_DX3GCR_RTTOAL_Msk (0x1U << DDRPHYC_DX3GCR_RTTOAL_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GCR_RTTOAL DDRPHYC_DX3GCR_RTTOAL_Msk /*!< RTT ON additive latency */ +#define DDRPHYC_DX3GCR_R0RVSL_Pos (14U) +#define DDRPHYC_DX3GCR_R0RVSL_Msk (0x7U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x0001C000 */ +#define DDRPHYC_DX3GCR_R0RVSL DDRPHYC_DX3GCR_R0RVSL_Msk /*!< Read valid system latency in steps */ +#define DDRPHYC_DX3GCR_R0RVSL_0 (0x1U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GCR_R0RVSL_1 (0x2U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3GCR_R0RVSL_2 (0x4U << DDRPHYC_DX3GCR_R0RVSL_Pos) /*!< 0x00010000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR0 register ****************/ +#define DDRPHYC_DX3GSR0_DTDONE_Pos (0U) +#define DDRPHYC_DX3GSR0_DTDONE_Msk (0x1U << DDRPHYC_DX3GSR0_DTDONE_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR0_DTDONE DDRPHYC_DX3GSR0_DTDONE_Msk /*!< Data training done */ +#define DDRPHYC_DX3GSR0_DTERR_Pos (4U) +#define DDRPHYC_DX3GSR0_DTERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTERR_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR0_DTERR DDRPHYC_DX3GSR0_DTERR_Msk /*!< DQS gate training error */ +#define DDRPHYC_DX3GSR0_DTIERR_Pos (8U) +#define DDRPHYC_DX3GSR0_DTIERR_Msk (0x1U << DDRPHYC_DX3GSR0_DTIERR_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3GSR0_DTIERR DDRPHYC_DX3GSR0_DTIERR_Msk /*!< DQS gate training intermittent error */ +#define DDRPHYC_DX3GSR0_DTPASS_Pos (13U) +#define DDRPHYC_DX3GSR0_DTPASS_Msk (0x7U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x0000E000 */ +#define DDRPHYC_DX3GSR0_DTPASS DDRPHYC_DX3GSR0_DTPASS_Msk /*!< DQS training pass count */ +#define DDRPHYC_DX3GSR0_DTPASS_0 (0x1U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3GSR0_DTPASS_1 (0x2U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3GSR0_DTPASS_2 (0x4U << DDRPHYC_DX3GSR0_DTPASS_Pos) /*!< 0x00008000 */ + +/*************** Bit definition for DDRPHYC_DX3GSR1 register ****************/ +#define DDRPHYC_DX3GSR1_DFTERR_Pos (0U) +#define DDRPHYC_DX3GSR1_DFTERR_Msk (0x1U << DDRPHYC_DX3GSR1_DFTERR_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3GSR1_DFTERR DDRPHYC_DX3GSR1_DFTERR_Msk /*!< DQS drift error */ +#define DDRPHYC_DX3GSR1_DQSDFT_Pos (4U) +#define DDRPHYC_DX3GSR1_DQSDFT_Msk (0x3U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000030 */ +#define DDRPHYC_DX3GSR1_DQSDFT DDRPHYC_DX3GSR1_DQSDFT_Msk /*!< DQS drift value */ +#define DDRPHYC_DX3GSR1_DQSDFT_0 (0x1U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3GSR1_DQSDFT_1 (0x2U << DDRPHYC_DX3GSR1_DQSDFT_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3GSR1_RVERR_Pos (12U) +#define DDRPHYC_DX3GSR1_RVERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVERR_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3GSR1_RVERR DDRPHYC_DX3GSR1_RVERR_Msk /*!< RV training error */ +#define DDRPHYC_DX3GSR1_RVIERR_Pos (16U) +#define DDRPHYC_DX3GSR1_RVIERR_Msk (0x1U << DDRPHYC_DX3GSR1_RVIERR_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3GSR1_RVIERR DDRPHYC_DX3GSR1_RVIERR_Msk /*!< RV intermittent error for rank */ +#define DDRPHYC_DX3GSR1_RVPASS_Pos (20U) +#define DDRPHYC_DX3GSR1_RVPASS_Msk (0x7U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3GSR1_RVPASS DDRPHYC_DX3GSR1_RVPASS_Msk /*!< Read valid training pass count */ +#define DDRPHYC_DX3GSR1_RVPASS_0 (0x1U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3GSR1_RVPASS_1 (0x2U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3GSR1_RVPASS_2 (0x4U << DDRPHYC_DX3GSR1_RVPASS_Pos) /*!< 0x00400000 */ + +/*************** Bit definition for DDRPHYC_DX3DLLCR register ***************/ +#define DDRPHYC_DX3DLLCR_SFBDLY_Pos (0U) +#define DDRPHYC_DX3DLLCR_SFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_SFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DLLCR_SFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFBDLY_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_Pos (3U) +#define DDRPHYC_DX3DLLCR_SFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000038 */ +#define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_SFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DLLCR_SFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_SFWDLY_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_Pos (6U) +#define DDRPHYC_DX3DLLCR_MFBDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x000001C0 */ +#define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-back trim */ +#define DDRPHYC_DX3DLLCR_MFBDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DLLCR_MFBDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFBDLY_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_Pos (9U) +#define DDRPHYC_DX3DLLCR_MFWDLY_Msk (0x7U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000E00 */ +#define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-forward trim */ +#define DDRPHYC_DX3DLLCR_MFWDLY_0 (0x1U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_1 (0x2U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DLLCR_MFWDLY_2 (0x4U << DDRPHYC_DX3DLLCR_MFWDLY_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DLLCR_SSTART_Pos (12U) +#define DDRPHYC_DX3DLLCR_SSTART_Msk (0x3U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DLLCR_SSTART DDRPHYC_DX3DLLCR_SSTART_Msk /*!< Slave DLL autostart */ +#define DDRPHYC_DX3DLLCR_SSTART_0 (0x1U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DLLCR_SSTART_1 (0x2U << DDRPHYC_DX3DLLCR_SSTART_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_Pos (14U) +#define DDRPHYC_DX3DLLCR_SDPHASE_Msk (0xFU << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x0003C000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE DDRPHYC_DX3DLLCR_SDPHASE_Msk /*!< Slave DLL phase */ +#define DDRPHYC_DX3DLLCR_SDPHASE_0 (0x1U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_1 (0x2U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_2 (0x4U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DLLCR_SDPHASE_3 (0x8U << DDRPHYC_DX3DLLCR_SDPHASE_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN_Pos (18U) +#define DDRPHYC_DX3DLLCR_ATESTEN_Msk (0x1U << DDRPHYC_DX3DLLCR_ATESTEN_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DLLCR_ATESTEN DDRPHYC_DX3DLLCR_ATESTEN_Msk /*!< Enable path to pin 'ATO' */ +#define DDRPHYC_DX3DLLCR_SDLBMODE_Pos (19U) +#define DDRPHYC_DX3DLLCR_SDLBMODE_Msk (0x1U << DDRPHYC_DX3DLLCR_SDLBMODE_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DLLCR_SDLBMODE DDRPHYC_DX3DLLCR_SDLBMODE_Msk /*!< Bypass slave DLL during loopback */ +#define DDRPHYC_DX3DLLCR_DLLSRST_Pos (30U) +#define DDRPHYC_DX3DLLCR_DLLSRST_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLSRST_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DLLCR_DLLSRST DDRPHYC_DX3DLLCR_DLLSRST_Msk /*!< DLL reset */ +#define DDRPHYC_DX3DLLCR_DLLDIS_Pos (31U) +#define DDRPHYC_DX3DLLCR_DLLDIS_Msk (0x1U << DDRPHYC_DX3DLLCR_DLLDIS_Pos) /*!< 0x80000000 */ +#define DDRPHYC_DX3DLLCR_DLLDIS DDRPHYC_DX3DLLCR_DLLDIS_Msk /*!< DLL bypass */ + +/*************** Bit definition for DDRPHYC_DX3DQTR register ****************/ +#define DDRPHYC_DX3DQTR_DQDLY0_Pos (0U) +#define DDRPHYC_DX3DQTR_DQDLY0_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x0000000F */ +#define DDRPHYC_DX3DQTR_DQDLY0 DDRPHYC_DX3DQTR_DQDLY0_Msk /*!< DQ delay for bit 0 */ +#define DDRPHYC_DX3DQTR_DQDLY0_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQTR_DQDLY0_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQTR_DQDLY0_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQTR_DQDLY0_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY0_Pos) /*!< 0x00000008 */ +#define DDRPHYC_DX3DQTR_DQDLY1_Pos (4U) +#define DDRPHYC_DX3DQTR_DQDLY1_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x000000F0 */ +#define DDRPHYC_DX3DQTR_DQDLY1 DDRPHYC_DX3DQTR_DQDLY1_Msk /*!< DQ delay for bit 1 */ +#define DDRPHYC_DX3DQTR_DQDLY1_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000010 */ +#define DDRPHYC_DX3DQTR_DQDLY1_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000020 */ +#define DDRPHYC_DX3DQTR_DQDLY1_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000040 */ +#define DDRPHYC_DX3DQTR_DQDLY1_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY1_Pos) /*!< 0x00000080 */ +#define DDRPHYC_DX3DQTR_DQDLY2_Pos (8U) +#define DDRPHYC_DX3DQTR_DQDLY2_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000F00 */ +#define DDRPHYC_DX3DQTR_DQDLY2 DDRPHYC_DX3DQTR_DQDLY2_Msk /*!< DQ delay for bit 2 */ +#define DDRPHYC_DX3DQTR_DQDLY2_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000100 */ +#define DDRPHYC_DX3DQTR_DQDLY2_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000200 */ +#define DDRPHYC_DX3DQTR_DQDLY2_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000400 */ +#define DDRPHYC_DX3DQTR_DQDLY2_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY2_Pos) /*!< 0x00000800 */ +#define DDRPHYC_DX3DQTR_DQDLY3_Pos (12U) +#define DDRPHYC_DX3DQTR_DQDLY3_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x0000F000 */ +#define DDRPHYC_DX3DQTR_DQDLY3 DDRPHYC_DX3DQTR_DQDLY3_Msk /*!< DQ delay for bit 3 */ +#define DDRPHYC_DX3DQTR_DQDLY3_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00004000 */ +#define DDRPHYC_DX3DQTR_DQDLY3_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY3_Pos) /*!< 0x00008000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_Pos (16U) +#define DDRPHYC_DX3DQTR_DQDLY4_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x000F0000 */ +#define DDRPHYC_DX3DQTR_DQDLY4 DDRPHYC_DX3DQTR_DQDLY4_Msk /*!< DQ delay for bit 4 */ +#define DDRPHYC_DX3DQTR_DQDLY4_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00010000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00020000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00040000 */ +#define DDRPHYC_DX3DQTR_DQDLY4_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY4_Pos) /*!< 0x00080000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_Pos (20U) +#define DDRPHYC_DX3DQTR_DQDLY5_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00F00000 */ +#define DDRPHYC_DX3DQTR_DQDLY5 DDRPHYC_DX3DQTR_DQDLY5_Msk /*!< DQ delay for bit 5 */ +#define DDRPHYC_DX3DQTR_DQDLY5_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQTR_DQDLY5_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY5_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_Pos (24U) +#define DDRPHYC_DX3DQTR_DQDLY6_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x0F000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6 DDRPHYC_DX3DQTR_DQDLY6_Msk /*!< DQ delay for bit 6 */ +#define DDRPHYC_DX3DQTR_DQDLY6_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQTR_DQDLY6_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY6_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_Pos (28U) +#define DDRPHYC_DX3DQTR_DQDLY7_Msk (0xFU << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0xF0000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7 DDRPHYC_DX3DQTR_DQDLY7_Msk /*!< DQ delay for bit 7 */ +#define DDRPHYC_DX3DQTR_DQDLY7_0 (0x1U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_1 (0x2U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x20000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_2 (0x4U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x40000000 */ +#define DDRPHYC_DX3DQTR_DQDLY7_3 (0x8U << DDRPHYC_DX3DQTR_DQDLY7_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for DDRPHYC_DX3DQSTR register ***************/ +#define DDRPHYC_DX3DQSTR_R0DGSL_Pos (0U) +#define DDRPHYC_DX3DQSTR_R0DGSL_Msk (0x7U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000007 */ +#define DDRPHYC_DX3DQSTR_R0DGSL DDRPHYC_DX3DQSTR_R0DGSL_Msk /*!< Rank 0 DQS gating system latency */ +#define DDRPHYC_DX3DQSTR_R0DGSL_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000001 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000002 */ +#define DDRPHYC_DX3DQSTR_R0DGSL_2 (0x4U << DDRPHYC_DX3DQSTR_R0DGSL_Pos) /*!< 0x00000004 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_Pos (12U) +#define DDRPHYC_DX3DQSTR_R0DGPS_Msk (0x3U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00003000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS DDRPHYC_DX3DQSTR_R0DGPS_Msk /*!< Rank 0 DQS gating phase select */ +#define DDRPHYC_DX3DQSTR_R0DGPS_0 (0x1U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00001000 */ +#define DDRPHYC_DX3DQSTR_R0DGPS_1 (0x2U << DDRPHYC_DX3DQSTR_R0DGPS_Pos) /*!< 0x00002000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_Pos (20U) +#define DDRPHYC_DX3DQSTR_DQSDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00700000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY DDRPHYC_DX3DQSTR_DQSDLY_Msk /*!< DQS delay */ +#define DDRPHYC_DX3DQSTR_DQSDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00100000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00200000 */ +#define DDRPHYC_DX3DQSTR_DQSDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSDLY_Pos) /*!< 0x00400000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_Pos (23U) +#define DDRPHYC_DX3DQSTR_DQSNDLY_Msk (0x7U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x03800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY DDRPHYC_DX3DQSTR_DQSNDLY_Msk /*!< DQS# delay */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x00800000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x01000000 */ +#define DDRPHYC_DX3DQSTR_DQSNDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DQSNDLY_Pos) /*!< 0x02000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_Pos (26U) +#define DDRPHYC_DX3DQSTR_DMDLY_Msk (0xFU << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x3C000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY DDRPHYC_DX3DQSTR_DMDLY_Msk /*!< DM delay */ +#define DDRPHYC_DX3DQSTR_DMDLY_0 (0x1U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x04000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_1 (0x2U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x08000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_2 (0x4U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x10000000 */ +#define DDRPHYC_DX3DQSTR_DMDLY_3 (0x8U << DDRPHYC_DX3DQSTR_DMDLY_Pos) /*!< 0x20000000 */ + /******************************************************************************/ /* */ /* Digital Filter for Sigma Delta Modulators */ @@ -19608,6 +24416,7 @@ typedef struct #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + /******************************************************************************/ /* */ /* Inter-Processor Communication Controller (IPCC) */ @@ -20289,7 +25098,7 @@ typedef struct #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */ #define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */ #define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */ -#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */ +#define MDMA_CTCR_SBURST_2 (0x4U << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */ #define MDMA_CTCR_DBURST_Pos (15U) #define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */ #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */ @@ -21170,766 +25979,2333 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for RCC_TZCR register********************/ -#define RCC_TZCR_TZEN_Pos (0U) -#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ -#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/ -#define RCC_TZCR_MCKPROT_Pos (1U) -#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ -#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/ - -/******************** Bit definition for RCC_OCENSETR register********************/ -#define RCC_OCENSETR_HSION_Pos (0U) -#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/ -#define RCC_OCENSETR_HSIKERON_Pos (1U) -#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_CSION_Pos (4U) -#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/ -#define RCC_OCENSETR_CSIKERON_Pos (5U) -#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_DIGBYP_Pos (7U) -#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/ -#define RCC_OCENSETR_HSEON_Pos (8U) -#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/ -#define RCC_OCENSETR_HSEKERON_Pos (9U) -#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/ -#define RCC_OCENSETR_HSEBYP_Pos (10U) -#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/ -#define RCC_OCENSETR_HSECSSON_Pos (11U) -#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ -#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/ - -/******************** Bit definition for RCC_OCENCLRR register********************/ -#define RCC_OCENCLRR_HSION_Pos (0U) -#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ -#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/ -#define RCC_OCENCLRR_HSIKERON_Pos (1U) -#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ -#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/ -#define RCC_OCENCLRR_CSION_Pos (4U) -#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ -#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/ -#define RCC_OCENCLRR_CSIKERON_Pos (5U) -#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ -#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/ -#define RCC_OCENCLRR_DIGBYP_Pos (7U) -#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */ -#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/ -#define RCC_OCENCLRR_HSEON_Pos (8U) -#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ -#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/ -#define RCC_OCENCLRR_HSEKERON_Pos (9U) -#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ -#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/ -#define RCC_OCENCLRR_HSEBYP_Pos (10U) -#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ -#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/ - -/******************** Bit definition for RCC_OCRDYR register********************/ -#define RCC_OCRDYR_HSIRDY_Pos (0U) -#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ -#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/ -#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) -#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ -#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/ -#define RCC_OCRDYR_CSIRDY_Pos (4U) -#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ -#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/ -#define RCC_OCRDYR_HSERDY_Pos (8U) -#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ -#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/ -#define RCC_OCRDYR_AXICKRDY_Pos (24U) -#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ -#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/ -#define RCC_OCRDYR_CKREST_Pos (25U) -#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ -#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/ - -/******************** Bit definition for RCC_DBGCFGR register********************/ -#define RCC_DBGCFGR_TRACEDIV_Pos (0U) -#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ -#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/ -#define RCC_DBGCFGR_DBGCKEN_Pos (8U) -#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ -#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/ -#define RCC_DBGCFGR_TRACECKEN_Pos (9U) -#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ -#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/ -#define RCC_DBGCFGR_DBGRST_Pos (12U) -#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ -#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/ - -/******************** Bit definition for RCC_HSICFGR register********************/ -#define RCC_HSICFGR_HSIDIV_Pos (0U) -#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) -#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/ -#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/ -#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */ -#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */ -#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */ - -#define RCC_HSICFGR_HSITRIM_Pos (8U) -#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos) -#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/ - -#define RCC_HSICFGR_HSICAL_Pos (16U) -#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) -#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/ - -/******************** Bit definition for RCC_CSICFGR register********************/ -#define RCC_CSICFGR_CSITRIM_Pos (8U) -#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) -#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/ - -#define RCC_CSICFGR_CSICAL_Pos (16U) -#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) -#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/ - -/******************** Bit definition for RCC_MCO1CFGR register********************/ -#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) -#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/ -#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ - -#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) -#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/ -#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO1CFGR_MCO1ON_Pos (12U) -#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/ - -/******************** Bit definition for RCC_MCO2CFGR register********************/ -#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) -#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ -#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/ -#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ -#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ -#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */ -#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ -#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */ - -#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) -#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ -#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/ -#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */ -#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ -#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ -#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */ -#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ -#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */ -#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */ -#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */ -#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ -#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */ -#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */ -#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */ -#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */ -#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */ -#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */ -#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ - -#define RCC_MCO2CFGR_MCO2ON_Pos (12U) -#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ -#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/ - -/******************** Bit definition for RCC_MPCKSELR register********************/ -#define RCC_MPCKSELR_MPUSRC_Pos (0U) -#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ -#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/ -#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */ -#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ -#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ -#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ - - -#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) -#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/ - -/******************** Bit definition for RCC_ASSCKSELR register********************/ -#define RCC_ASSCKSELR_AXISSRC_Pos (0U) -#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ -#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/ -#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */ -#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ -#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ -#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */ -#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ -#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */ -#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */ -#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ - -#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) -#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/ - -/******************** Bit definition for RCC_MSSCKSELR register********************/ -#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) -#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ -#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/ -#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */ -#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ -#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ -#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ - -#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) -#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/ - -/******************** Bit definition for RCC_RCK12SELR register********************/ -#define RCC_RCK12SELR_PLL12SRC_Pos (0U) -#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/ -#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */ -#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */ -#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */ -#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */ - -#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) -#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK3SELR register********************/ -#define RCC_RCK3SELR_PLL3SRC_Pos (0U) -#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/ -#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) -#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/ - -/******************** Bit definition for RCC_RCK4SELR register********************/ -#define RCC_RCK4SELR_PLL4SRC_Pos (0U) -#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ -#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/ -#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */ -#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ -#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ -#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ - -#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) -#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ -#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/ - -/******************** Bit definition for RCC_TIMG1PRER register********************/ -#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) -#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal to - 2 x Fck_pclk1 (default after reset)*/ -#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk1 */ - -#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) -#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_TIMG2PRER register********************/ -#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) -#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ -#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/ -#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */ - /*corresponding to a division by 1 or 2, else it is equal - to 2 x Fck_pclk2 (default after reset)*/ -#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is - corresponding to division by 1, 2 or 4, else it is equal to - 4 x Fck_pclk2 */ - -#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) -#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ -#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/ - -/******************** Bit definition for RCC_RTCDIVR register********************/ -#define RCC_RTCDIVR_RTCDIV_Pos (0U) -#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ -#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/ -#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos) -#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) - -#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/ - -/******************** Bit definition for RCC_MPCKDIVR register********************/ -#define RCC_MPCKDIVR_MPUDIV_Pos (0U) -#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/ -#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ - -#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) -#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/ - -/******************** Bit definition for RCC_AXIDIVR register********************/ -#define RCC_AXIDIVR_AXIDIV_Pos (0U) -#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ -#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/ -#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */ -#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ -#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ -#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */ -#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ -#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */ -#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */ -#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ - -#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) -#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/ - -/******************** Bit definition for RCC_APB4DIVR register********************/ -#define RCC_APB4DIVR_APB4DIV_Pos (0U) -#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */ -#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) -#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/ - -/******************** Bit definition for RCC_APB5DIVR register********************/ -#define RCC_APB5DIVR_APB5DIV_Pos (0U) -#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/ -#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ -#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */ -#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */ -#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ - -#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) -#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/ - -/******************** Bit definition for RCC_MCUDIVR register********************/ -#define RCC_MCUDIVR_MCUDIV_Pos (0U) -#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ -#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/ -#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */ -#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ -#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ -#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */ -#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ -#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */ -#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */ -#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */ -#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ -#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */ -/* @note others: ck_mcuss divided by 512 */ - -#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) -#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/ -/******************** Bit definition for RCC_APB1DIVR register********************/ -#define RCC_APB1DIVR_APB1DIV_Pos (0U) -#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/ -#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) -#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/ - -/******************** Bit definition for RCC_APB2DIV register********************/ -#define RCC_APB2DIVR_APB2DIV_Pos (0U) -#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/ -#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) -#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/ - -/******************** Bit definition for RCC_APB3DIV register********************/ -#define RCC_APB3DIVR_APB3DIV_Pos (0U) -#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ -#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/ -#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */ -#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ -#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ -#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */ -#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ -/* @note others: ck_hclk/16 */ - -#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) -#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ -#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/ - -/******************** Bit definition for RCC_PLL1CR register********************/ -#define RCC_PLL1CR_PLLON_Pos (0U) -#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/ -#define RCC_PLL1CR_PLL1RDY_Pos (1U) -#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/ -#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/ -#define RCC_PLL1CR_DIVPEN_Pos (4U) -#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/ -#define RCC_PLL1CR_DIVQEN_Pos (5U) -#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/ -#define RCC_PLL1CR_DIVREN_Pos (6U) -#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL1CFGR1 register********************/ -#define RCC_PLL1CFGR1_DIVN_Pos (0U) -#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL1CFGR1_DIVM1_Pos (16U) -#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ -#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/ - -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL1CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL1CFGR2_DIVP_Pos (0U) -#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/ -#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL1CFGR2_DIVQ_Pos (8U) -#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/ -#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL1CFGR2_DIVR_Pos (16U) -#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/ -#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL1FRACR register********************/ -#define RCC_PLL1FRACR_FRACV_Pos (3U) -#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL1FRACR_FRACLE_Pos (16U) -#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL1CSGR register********************/ -#define RCC_PLL1CSGR_MOD_PER_Pos (0U) -#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/ -#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL1CSGR_INC_STEP_Pos (16U) -#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/ - -/******************** Bit definition for RCC_PLL2CR register********************/ -#define RCC_PLL2CR_PLLON_Pos (0U) -#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/ -#define RCC_PLL2CR_PLL2RDY_Pos (1U) -#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/ -#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/ -#define RCC_PLL2CR_DIVPEN_Pos (4U) -#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/ -#define RCC_PLL2CR_DIVQEN_Pos (5U) -#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/ -#define RCC_PLL2CR_DIVREN_Pos (6U) -#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/ -/******************** Bit definition for RCC_PLL2CFGR1 register********************/ -#define RCC_PLL2CFGR1_DIVN_Pos (0U) -#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/ -/* @note Valid division rations for DIVN: between 25 and 100 */ -#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */ - -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Pos (16U) -#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ -#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -/******************** Bit definition for RCC_PLL2CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL2CFGR2_DIVP_Pos (0U) -#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/ -#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL2CFGR2_DIVQ_Pos (8U) -#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/ -#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL2CFGR2_DIVR_Pos (16U) -#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/ -#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL2FRACR register********************/ -#define RCC_PLL2FRACR_FRACV_Pos (3U) -#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL2FRACR_FRACLE_Pos (16U) -#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/ - -/******************** Bit definition for RCC_PLL2CSGR register********************/ -#define RCC_PLL2CSGR_MOD_PER_Pos (0U) -#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ -#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/ -#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) -#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ -#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/ -#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) -#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ -#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/ -#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) -#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ -#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ -#define RCC_PLL2CSGR_INC_STEP_Pos (16U) -#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ -#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/ - -/******************** Bit definition for RCC_PLL3CR register********************/ -#define RCC_PLL3CR_PLLON_Pos (0U) -#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/ -#define RCC_PLL3CR_PLL3RDY_Pos (1U) -#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/ -#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/ -#define RCC_PLL3CR_DIVPEN_Pos (4U) -#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/ -#define RCC_PLL3CR_DIVQEN_Pos (5U) -#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/ -#define RCC_PLL3CR_DIVREN_Pos (6U) -#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL3CFGR1 register********************/ -#define RCC_PLL3CFGR1_DIVN_Pos (0U) -#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - - -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Pos (16U) -#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ -#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL3CFGR1_IFRGE_Pos (24U) -#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/ -#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /* between 4 and 8 MHz (default after reset) */ -#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL3CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL3CFGR2_DIVP_Pos (0U) -#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/ -#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL3CFGR2_DIVQ_Pos (8U) -#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/ -#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL3CFGR2_DIVR_Pos (16U) -#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/ -#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL3FRACR register********************/ -#define RCC_PLL3FRACR_FRACV_Pos (3U) -#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL3FRACR_FRACLE_Pos (16U) -#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/ +#define RCC_TZCR_TZEN_Pos (0U) +#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */ +#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*!< RCC TrustZone (secure) Enable */ +#define RCC_TZCR_MCKPROT_Pos (1U) +#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */ +#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*!< Protection of the generation of mcuss_ck clock (secure) Enable */ + +/***************** Bit definition for RCC_OCENSETR register *****************/ +#define RCC_OCENSETR_HSION_Pos (0U) +#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*!< Set HSION bit */ +#define RCC_OCENSETR_HSIKERON_Pos (1U) +#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*!< Set HSIKERON bit */ +#define RCC_OCENSETR_CSION_Pos (4U) +#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*!< Set CSION bit */ +#define RCC_OCENSETR_CSIKERON_Pos (5U) +#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*!< Set CSIKERON bit */ +#define RCC_OCENSETR_DIGBYP_Pos (7U) +#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*!< Set DIGBYP bit */ +#define RCC_OCENSETR_HSEON_Pos (8U) +#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*!< Set HSEON bit */ +#define RCC_OCENSETR_HSEKERON_Pos (9U) +#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*!< Set HSEKERON bit */ +#define RCC_OCENSETR_HSEBYP_Pos (10U) +#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*!< Set HSEBYP bit */ +#define RCC_OCENSETR_HSECSSON_Pos (11U) +#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */ +#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*!< Set the HSECSSON bit */ + +/***************** Bit definition for RCC_OCENCLRR register *****************/ +#define RCC_OCENCLRR_HSION_Pos (0U) +#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*!< Clear of HSION bit */ +#define RCC_OCENCLRR_HSIKERON_Pos (1U) +#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*!< Clear of HSIKERON bit */ +#define RCC_OCENCLRR_CSION_Pos (4U) +#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */ +#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*!< Clear of CSION bit */ +#define RCC_OCENCLRR_CSIKERON_Pos (5U) +#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */ +#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*!< Clear of CSIKERON bit */ +#define RCC_OCENCLRR_DIGBYP_Pos (7U) +#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000080 */ +#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*!< Clear of DIGBYP bit */ +#define RCC_OCENCLRR_HSEON_Pos (8U) +#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */ +#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*!< Clear of HSEON bit */ +#define RCC_OCENCLRR_HSEKERON_Pos (9U) +#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */ +#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*!< Clear HSEKERON bit */ +#define RCC_OCENCLRR_HSEBYP_Pos (10U) +#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */ +#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*!< Clear the HSEBYP bit */ + +/***************** Bit definition for RCC_HSICFGR register ******************/ +#define RCC_HSICFGR_HSIDIV_Pos (0U) +#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000003 */ +#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */ +#define RCC_HSICFGR_HSIDIV_0 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSIDIV_1 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSITRIM_Pos (8U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FU << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */ +#define RCC_HSICFGR_HSITRIM_0 (0x1U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSITRIM_1 (0x2U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSITRIM_2 (0x4U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSITRIM_3 (0x8U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40U << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x00004000 */ +#define RCC_HSICFGR_HSICAL_Pos (16U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos) /*!< 0x0FFF0000 */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */ +#define RCC_HSICFGR_HSICAL_0 (0x1U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00010000 */ +#define RCC_HSICFGR_HSICAL_1 (0x2U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00020000 */ +#define RCC_HSICFGR_HSICAL_2 (0x4U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00040000 */ +#define RCC_HSICFGR_HSICAL_3 (0x8U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00080000 */ +#define RCC_HSICFGR_HSICAL_4 (0x10U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00100000 */ +#define RCC_HSICFGR_HSICAL_5 (0x20U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00200000 */ +#define RCC_HSICFGR_HSICAL_6 (0x40U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00400000 */ +#define RCC_HSICFGR_HSICAL_7 (0x80U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00800000 */ +#define RCC_HSICFGR_HSICAL_8 (0x100U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSICAL_9 (0x200U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSICAL_10 (0x400U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSICAL_11 (0x800U << RCC_HSICFGR_HSICAL_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for RCC_CSICFGR register ******************/ +#define RCC_CSICFGR_CSITRIM_Pos (8U) +#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001F00 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSI clock trimming */ +#define RCC_CSICFGR_CSITRIM_0 (0x1U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_CSICFGR_CSITRIM_1 (0x2U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_CSICFGR_CSITRIM_2 (0x4U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_CSICFGR_CSITRIM_3 (0x8U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10U << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_CSICFGR_CSICAL_Pos (16U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00FF0000 */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSI clock calibration */ +#define RCC_CSICFGR_CSICAL_0 (0x1U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00010000 */ +#define RCC_CSICFGR_CSICAL_1 (0x2U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00020000 */ +#define RCC_CSICFGR_CSICAL_2 (0x4U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00040000 */ +#define RCC_CSICFGR_CSICAL_3 (0x8U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00080000 */ +#define RCC_CSICFGR_CSICAL_4 (0x10U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00100000 */ +#define RCC_CSICFGR_CSICAL_5 (0x20U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00200000 */ +#define RCC_CSICFGR_CSICAL_6 (0x40U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00400000 */ +#define RCC_CSICFGR_CSICAL_7 (0x80U << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00800000 */ + +/***************** Bit definition for RCC_MPCKSELR register *****************/ +#define RCC_MPCKSELR_MPUSRC_Pos (0U) +#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */ +#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*!< MPU clock switch */ +#define RCC_MPCKSELR_MPUSRC_0 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */ +#define RCC_MPCKSELR_MPUSRC_1 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */ +#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U) +#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*!< MPU clock switch status */ + +/**************** Bit definition for RCC_ASSCKSELR register *****************/ +#define RCC_ASSCKSELR_AXISSRC_Pos (0U) +#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */ +#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */ +#define RCC_ASSCKSELR_AXISSRC_0 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */ +#define RCC_ASSCKSELR_AXISSRC_1 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */ +#define RCC_ASSCKSELR_AXISSRC_2 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */ +#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U) +#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch status */ + +/**************** Bit definition for RCC_RCK12SELR register *****************/ +#define RCC_RCK12SELR_PLL12SRC_Pos (0U) +#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*!< Reference clock selection for PLL1 and PLL2 */ +#define RCC_RCK12SELR_PLL12SRC_0 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK12SELR_PLL12SRC_1 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U) +#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*!< PLL12 reference clock switch status */ + +/***************** Bit definition for RCC_MPCKDIVR register *****************/ +#define RCC_MPCKDIVR_MPUDIV_Pos (0U) +#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */ +#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*!< MPU Core clock divider */ +#define RCC_MPCKDIVR_MPUDIV_0 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MPCKDIVR_MPUDIV_1 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MPCKDIVR_MPUDIV_2 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U) +#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider status */ + +/***************** Bit definition for RCC_AXIDIVR register ******************/ +#define RCC_AXIDIVR_AXIDIV_Pos (0U) +#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */ +#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*!< AXI, AHB5 and AHB6 clock divider */ +#define RCC_AXIDIVR_AXIDIV_0 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */ +#define RCC_AXIDIVR_AXIDIV_1 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */ +#define RCC_AXIDIVR_AXIDIV_2 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */ +#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U) +#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider status */ + +/***************** Bit definition for RCC_APB4DIVR register *****************/ +#define RCC_APB4DIVR_APB4DIV_Pos (0U) +#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*!< APB4 clock divider */ +#define RCC_APB4DIVR_APB4DIV_0 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB4DIVR_APB4DIV_1 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB4DIVR_APB4DIV_2 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U) +#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*!< APB4 clock divider status */ + +/***************** Bit definition for RCC_APB5DIVR register *****************/ +#define RCC_APB5DIVR_APB5DIV_Pos (0U) +#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*!< APB5 clock divider */ +#define RCC_APB5DIVR_APB5DIV_0 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB5DIVR_APB5DIV_1 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB5DIVR_APB5DIV_2 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U) +#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*!< APB5 clock divider status */ + +/***************** Bit definition for RCC_RTCDIVR register ******************/ +#define RCC_RTCDIVR_RTCDIV_Pos (0U) +#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */ +#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*!< HSE division factor for RTC clock */ +#define RCC_RTCDIVR_RTCDIV_0 (0x1U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000001 */ +#define RCC_RTCDIVR_RTCDIV_1 (0x2U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000002 */ +#define RCC_RTCDIVR_RTCDIV_2 (0x4U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000004 */ +#define RCC_RTCDIVR_RTCDIV_3 (0x8U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000008 */ +#define RCC_RTCDIVR_RTCDIV_4 (0x10U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000010 */ +#define RCC_RTCDIVR_RTCDIV_5 (0x20U << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x00000020 */ + +/**************** Bit definition for RCC_MSSCKSELR register *****************/ +#define RCC_MSSCKSELR_MCUSSRC_Pos (0U) +#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */ +#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*!< MCUSS clock switch */ +#define RCC_MSSCKSELR_MCUSSRC_0 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */ +#define RCC_MSSCKSELR_MCUSSRC_1 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */ +#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U) +#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch status */ + +/****************** Bit definition for RCC_PLL1CR register ******************/ +#define RCC_PLL1CR_PLLON_Pos (0U) +#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*!< PLL1 enable */ +#define RCC_PLL1CR_PLL1RDY_Pos (1U) +#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*!< PLL1 clock ready flag */ +#define RCC_PLL1CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*!< Spread Spectrum Clock Generator of PLL1 enable */ +#define RCC_PLL1CR_DIVPEN_Pos (4U) +#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLL1CR_DIVQEN_Pos (5U) +#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLL1CR_DIVREN_Pos (6U) +#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*!< PLL1 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL1CFGR1 register *****************/ +#define RCC_PLL1CFGR1_DIVN_Pos (0U) +#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*!< Multiplication factor for PLL1 VCO */ +#define RCC_PLL1CFGR1_DIVN_0 (0x1U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR1_DIVN_1 (0x2U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR1_DIVN_2 (0x4U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR1_DIVN_3 (0x8U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR1_DIVN_4 (0x10U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR1_DIVN_5 (0x20U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR1_DIVN_6 (0x40U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR1_DIVN_7 (0x80U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CFGR1_DIVN_8 (0x100U << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR1_DIVM1_Pos (16U) +#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */ +#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*!< Prescaler for PLL1 */ +#define RCC_PLL1CFGR1_DIVM1_0 (0x1U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR1_DIVM1_1 (0x2U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR1_DIVM1_2 (0x4U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR1_DIVM1_3 (0x8U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR1_DIVM1_4 (0x10U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR1_DIVM1_5 (0x20U << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL1CFGR2 register *****************/ +#define RCC_PLL1CFGR2_DIVP_Pos (0U) +#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*!< PLL1 DIVP division factor */ +#define RCC_PLL1CFGR2_DIVP_0 (0x1U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR2_DIVP_1 (0x2U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR2_DIVP_2 (0x4U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR2_DIVP_3 (0x8U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR2_DIVP_4 (0x10U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR2_DIVP_5 (0x20U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CFGR2_DIVP_6 (0x40U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CFGR2_DIVQ_Pos (8U) +#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*!< PLL1 DIVQ division factor */ +#define RCC_PLL1CFGR2_DIVQ_0 (0x1U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR2_DIVQ_1 (0x2U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR2_DIVQ_2 (0x4U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR2_DIVQ_3 (0x8U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CFGR2_DIVQ_4 (0x10U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CFGR2_DIVQ_5 (0x20U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CFGR2_DIVQ_6 (0x40U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CFGR2_DIVR_Pos (16U) +#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*!< PLL1 DIVR division factor */ +#define RCC_PLL1CFGR2_DIVR_0 (0x1U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR2_DIVR_1 (0x2U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR2_DIVR_2 (0x4U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR2_DIVR_3 (0x8U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CFGR2_DIVR_4 (0x10U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR2_DIVR_5 (0x20U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR2_DIVR_6 (0x40U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL1FRACR register *****************/ +#define RCC_PLL1FRACR_FRACV_Pos (3U) +#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL1 VCO */ +#define RCC_PLL1FRACR_FRACV_0 (0x1U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL1FRACR_FRACV_1 (0x2U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL1FRACR_FRACV_2 (0x4U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL1FRACR_FRACV_3 (0x8U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL1FRACR_FRACV_4 (0x10U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL1FRACR_FRACV_5 (0x20U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL1FRACR_FRACV_6 (0x40U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL1FRACR_FRACV_7 (0x80U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL1FRACR_FRACV_8 (0x100U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL1FRACR_FRACV_9 (0x200U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL1FRACR_FRACV_10 (0x400U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL1FRACR_FRACV_11 (0x800U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL1FRACR_FRACV_12 (0x1000U << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL1FRACR_FRACLE_Pos (16U) +#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*!< PLL1 fractional latch enable */ + +/***************** Bit definition for RCC_PLL1CSGR register *****************/ +#define RCC_PLL1CSGR_MOD_PER_Pos (0U) +#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL1 */ +#define RCC_PLL1CSGR_MOD_PER_0 (0x1U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CSGR_MOD_PER_1 (0x2U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CSGR_MOD_PER_2 (0x4U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CSGR_MOD_PER_3 (0x8U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CSGR_MOD_PER_4 (0x10U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CSGR_MOD_PER_5 (0x20U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1CSGR_MOD_PER_6 (0x40U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1CSGR_MOD_PER_7 (0x80U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1CSGR_MOD_PER_8 (0x100U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CSGR_MOD_PER_9 (0x200U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CSGR_MOD_PER_10 (0x400U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CSGR_MOD_PER_11 (0x800U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1CSGR_MOD_PER_12 (0x1000U << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL1CSGR_INC_STEP_Pos (16U) +#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL1 */ +#define RCC_PLL1CSGR_INC_STEP_0 (0x1U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CSGR_INC_STEP_1 (0x2U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CSGR_INC_STEP_2 (0x4U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CSGR_INC_STEP_3 (0x8U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1CSGR_INC_STEP_4 (0x10U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CSGR_INC_STEP_5 (0x20U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CSGR_INC_STEP_6 (0x40U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CSGR_INC_STEP_7 (0x80U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1CSGR_INC_STEP_8 (0x100U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1CSGR_INC_STEP_9 (0x200U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1CSGR_INC_STEP_10 (0x400U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1CSGR_INC_STEP_11 (0x800U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1CSGR_INC_STEP_12 (0x1000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1CSGR_INC_STEP_13 (0x2000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1CSGR_INC_STEP_14 (0x4000U << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/****************** Bit definition for RCC_PLL2CR register ******************/ +#define RCC_PLL2CR_PLLON_Pos (0U) +#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*!< PLL2 enable */ +#define RCC_PLL2CR_PLL2RDY_Pos (1U) +#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ +#define RCC_PLL2CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL2 enable */ +#define RCC_PLL2CR_DIVPEN_Pos (4U) +#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLL2CR_DIVQEN_Pos (5U) +#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLL2CR_DIVREN_Pos (6U) +#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*!< PLL2 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL2CFGR1 register *****************/ +#define RCC_PLL2CFGR1_DIVN_Pos (0U) +#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*!< Multiplication factor for PLL2 VCO */ +#define RCC_PLL2CFGR1_DIVN_0 (0x1U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR1_DIVN_1 (0x2U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR1_DIVN_2 (0x4U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR1_DIVN_3 (0x8U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR1_DIVN_4 (0x10U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR1_DIVN_5 (0x20U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR1_DIVN_6 (0x40U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR1_DIVN_7 (0x80U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CFGR1_DIVN_8 (0x100U << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR1_DIVM2_Pos (16U) +#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */ +#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*!< Prescaler for PLL2 */ +#define RCC_PLL2CFGR1_DIVM2_0 (0x1U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR1_DIVM2_1 (0x2U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR1_DIVM2_2 (0x4U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR1_DIVM2_3 (0x8U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR1_DIVM2_4 (0x10U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR1_DIVM2_5 (0x20U << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x00200000 */ + +/**************** Bit definition for RCC_PLL2CFGR2 register *****************/ +#define RCC_PLL2CFGR2_DIVP_Pos (0U) +#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*!< PLL2 DIVP division factor */ +#define RCC_PLL2CFGR2_DIVP_0 (0x1U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CFGR2_DIVP_1 (0x2U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CFGR2_DIVP_2 (0x4U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CFGR2_DIVP_3 (0x8U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CFGR2_DIVP_4 (0x10U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CFGR2_DIVP_5 (0x20U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CFGR2_DIVP_6 (0x40U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CFGR2_DIVQ_Pos (8U) +#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*!< PLL2 DIVQ division factor */ +#define RCC_PLL2CFGR2_DIVQ_0 (0x1U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CFGR2_DIVQ_1 (0x2U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CFGR2_DIVQ_2 (0x4U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CFGR2_DIVQ_3 (0x8U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CFGR2_DIVQ_4 (0x10U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CFGR2_DIVQ_5 (0x20U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CFGR2_DIVQ_6 (0x40U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CFGR2_DIVR_Pos (16U) +#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*!< PLL2 DIVR division factor */ +#define RCC_PLL2CFGR2_DIVR_0 (0x1U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CFGR2_DIVR_1 (0x2U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CFGR2_DIVR_2 (0x4U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CFGR2_DIVR_3 (0x8U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CFGR2_DIVR_4 (0x10U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CFGR2_DIVR_5 (0x20U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CFGR2_DIVR_6 (0x40U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL2FRACR register *****************/ +#define RCC_PLL2FRACR_FRACV_Pos (3U) +#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL2 VCO */ +#define RCC_PLL2FRACR_FRACV_0 (0x1U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL2FRACR_FRACV_1 (0x2U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL2FRACR_FRACV_2 (0x4U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL2FRACR_FRACV_3 (0x8U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL2FRACR_FRACV_4 (0x10U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL2FRACR_FRACV_5 (0x20U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL2FRACR_FRACV_6 (0x40U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL2FRACR_FRACV_7 (0x80U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL2FRACR_FRACV_8 (0x100U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL2FRACR_FRACV_9 (0x200U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL2FRACR_FRACV_10 (0x400U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL2FRACR_FRACV_11 (0x800U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL2FRACR_FRACV_12 (0x1000U << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL2FRACR_FRACLE_Pos (16U) +#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*!< PLL2 fractional latch enable */ + +/***************** Bit definition for RCC_PLL2CSGR register *****************/ +#define RCC_PLL2CSGR_MOD_PER_Pos (0U) +#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*!< Modulation Period Adjustment for PLL2 */ +#define RCC_PLL2CSGR_MOD_PER_0 (0x1U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2CSGR_MOD_PER_1 (0x2U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2CSGR_MOD_PER_2 (0x4U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2CSGR_MOD_PER_3 (0x8U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2CSGR_MOD_PER_4 (0x10U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2CSGR_MOD_PER_5 (0x20U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2CSGR_MOD_PER_6 (0x40U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2CSGR_MOD_PER_7 (0x80U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2CSGR_MOD_PER_8 (0x100U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2CSGR_MOD_PER_9 (0x200U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2CSGR_MOD_PER_10 (0x400U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2CSGR_MOD_PER_11 (0x800U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2CSGR_MOD_PER_12 (0x1000U << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U) +#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*!< Dithering TPDF noise control */ +#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U) +#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*!< Dithering RPDF noise control */ +#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U) +#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */ +#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*!< Spread spectrum clock generator mode */ +#define RCC_PLL2CSGR_INC_STEP_Pos (16U) +#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*!< Modulation Depth Adjustment for PLL2 */ +#define RCC_PLL2CSGR_INC_STEP_0 (0x1U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2CSGR_INC_STEP_1 (0x2U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2CSGR_INC_STEP_2 (0x4U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2CSGR_INC_STEP_3 (0x8U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2CSGR_INC_STEP_4 (0x10U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2CSGR_INC_STEP_5 (0x20U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2CSGR_INC_STEP_6 (0x40U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2CSGR_INC_STEP_7 (0x80U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2CSGR_INC_STEP_8 (0x100U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2CSGR_INC_STEP_9 (0x200U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2CSGR_INC_STEP_10 (0x400U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2CSGR_INC_STEP_11 (0x800U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2CSGR_INC_STEP_12 (0x1000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2CSGR_INC_STEP_13 (0x2000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2CSGR_INC_STEP_14 (0x4000U << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x40000000 */ + +/*************** Bit definition for RCC_I2C46CKSELR register ****************/ +#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) +#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*!< I2C4 and I2C6 kernel clock source selection */ +#define RCC_I2C46CKSELR_I2C46SRC_0 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C46CKSELR_I2C46SRC_1 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C46CKSELR_I2C46SRC_2 (0x4U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SPI6CKSELR register ****************/ +#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) +#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*!< SPI6 kernel clock source selection */ +#define RCC_SPI6CKSELR_SPI6SRC_0 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI6CKSELR_SPI6SRC_1 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI6CKSELR_SPI6SRC_2 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART1CKSELR register ****************/ +#define RCC_UART1CKSELR_UART1SRC_Pos (0U) +#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*!< UART1 kernel clock source selection */ +#define RCC_UART1CKSELR_UART1SRC_0 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART1CKSELR_UART1SRC_1 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART1CKSELR_UART1SRC_2 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_RNG1CKSELR register ****************/ +#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) +#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*!< RNG1 kernel clock source selection */ +#define RCC_RNG1CKSELR_RNG1SRC_0 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG1CKSELR_RNG1SRC_1 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CPERCKSELR register ****************/ +#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) +#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ +#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_CPERCKSELR_CKPERSRC_0 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ +#define RCC_CPERCKSELR_CKPERSRC_1 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_STGENCKSELR register ****************/ +#define RCC_STGENCKSELR_STGENSRC_Pos (0U) +#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ +#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*!< Oscillator selection for kernel clock */ +#define RCC_STGENCKSELR_STGENSRC_0 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ +#define RCC_STGENCKSELR_STGENSRC_1 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ + +/***************** Bit definition for RCC_DDRITFCR register *****************/ +#define RCC_DDRITFCR_DDRC1EN_Pos (0U) +#define RCC_DDRITFCR_DDRC1EN_Msk (0x1U << RCC_DDRITFCR_DDRC1EN_Pos) /*!< 0x00000001 */ +#define RCC_DDRITFCR_DDRC1EN RCC_DDRITFCR_DDRC1EN_Msk /*!< DDRC port 1 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC1LPEN_Pos (1U) +#define RCC_DDRITFCR_DDRC1LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC1LPEN_Pos) /*!< 0x00000002 */ +#define RCC_DDRITFCR_DDRC1LPEN RCC_DDRITFCR_DDRC1LPEN_Msk /*!< DDRC port 1 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRC2EN_Pos (2U) +#define RCC_DDRITFCR_DDRC2EN_Msk (0x1U << RCC_DDRITFCR_DDRC2EN_Pos) /*!< 0x00000004 */ +#define RCC_DDRITFCR_DDRC2EN RCC_DDRITFCR_DDRC2EN_Msk /*!< DDRC port 2 peripheral clocks enable */ +#define RCC_DDRITFCR_DDRC2LPEN_Pos (3U) +#define RCC_DDRITFCR_DDRC2LPEN_Msk (0x1U << RCC_DDRITFCR_DDRC2LPEN_Pos) /*!< 0x00000008 */ +#define RCC_DDRITFCR_DDRC2LPEN RCC_DDRITFCR_DDRC2LPEN_Msk /*!< DDRC port 2 peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRPHYCEN_Pos (4U) +#define RCC_DDRITFCR_DDRPHYCEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCEN_Pos) /*!< 0x00000010 */ +#define RCC_DDRITFCR_DDRPHYCEN RCC_DDRITFCR_DDRPHYCEN_Msk /*!< DDRPHYC peripheral clocks enable */ +#define RCC_DDRITFCR_DDRPHYCLPEN_Pos (5U) +#define RCC_DDRITFCR_DDRPHYCLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCLPEN_Pos) /*!< 0x00000020 */ +#define RCC_DDRITFCR_DDRPHYCLPEN RCC_DDRITFCR_DDRPHYCLPEN_Msk /*!< DDRPHYC peripheral clocks enable during CSleep mode */ +#define RCC_DDRITFCR_DDRCAPBEN_Pos (6U) +#define RCC_DDRITFCR_DDRCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBEN_Pos) /*!< 0x00000040 */ +#define RCC_DDRITFCR_DDRCAPBEN RCC_DDRITFCR_DDRCAPBEN_Msk /*!< DDRC APB clock enable */ +#define RCC_DDRITFCR_DDRCAPBLPEN_Pos (7U) +#define RCC_DDRITFCR_DDRCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRCAPBLPEN_Pos) /*!< 0x00000080 */ +#define RCC_DDRITFCR_DDRCAPBLPEN RCC_DDRITFCR_DDRCAPBLPEN_Msk /*!< DDRC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_AXIDCGEN_Pos (8U) +#define RCC_DDRITFCR_AXIDCGEN_Msk (0x1U << RCC_DDRITFCR_AXIDCGEN_Pos) /*!< 0x00000100 */ +#define RCC_DDRITFCR_AXIDCGEN RCC_DDRITFCR_AXIDCGEN_Msk /*!< AXIDCG enable during MPU CRun mode */ +#define RCC_DDRITFCR_DDRPHYCAPBEN_Pos (9U) +#define RCC_DDRITFCR_DDRPHYCAPBEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBEN_Pos) /*!< 0x00000200 */ +#define RCC_DDRITFCR_DDRPHYCAPBEN RCC_DDRITFCR_DDRPHYCAPBEN_Msk /*!< DDRPHYC APB clock enable */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos (10U) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk (0x1U << RCC_DDRITFCR_DDRPHYCAPBLPEN_Pos) /*!< 0x00000400 */ +#define RCC_DDRITFCR_DDRPHYCAPBLPEN RCC_DDRITFCR_DDRPHYCAPBLPEN_Msk /*!< DDRPHYC APB clock enable during CSleep mode */ +#define RCC_DDRITFCR_KERDCG_DLY_Pos (11U) +#define RCC_DDRITFCR_KERDCG_DLY_Msk (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ +#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*!< AXIDCG delay */ +#define RCC_DDRITFCR_KERDCG_DLY_0 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ +#define RCC_DDRITFCR_KERDCG_DLY_1 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ +#define RCC_DDRITFCR_KERDCG_DLY_2 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ +#define RCC_DDRITFCR_DDRCAPBRST_Pos (14U) +#define RCC_DDRITFCR_DDRCAPBRST_Msk (0x1U << RCC_DDRITFCR_DDRCAPBRST_Pos) /*!< 0x00004000 */ +#define RCC_DDRITFCR_DDRCAPBRST RCC_DDRITFCR_DDRCAPBRST_Msk /*!< DDRC APB interface reset */ +#define RCC_DDRITFCR_DDRCAXIRST_Pos (15U) +#define RCC_DDRITFCR_DDRCAXIRST_Msk (0x1U << RCC_DDRITFCR_DDRCAXIRST_Pos) /*!< 0x00008000 */ +#define RCC_DDRITFCR_DDRCAXIRST RCC_DDRITFCR_DDRCAXIRST_Msk /*!< DDRC AXI interface reset */ +#define RCC_DDRITFCR_DDRCORERST_Pos (16U) +#define RCC_DDRITFCR_DDRCORERST_Msk (0x1U << RCC_DDRITFCR_DDRCORERST_Pos) /*!< 0x00010000 */ +#define RCC_DDRITFCR_DDRCORERST RCC_DDRITFCR_DDRCORERST_Msk /*!< DDRC core reset */ +#define RCC_DDRITFCR_DPHYAPBRST_Pos (17U) +#define RCC_DDRITFCR_DPHYAPBRST_Msk (0x1U << RCC_DDRITFCR_DPHYAPBRST_Pos) /*!< 0x00020000 */ +#define RCC_DDRITFCR_DPHYAPBRST RCC_DDRITFCR_DPHYAPBRST_Msk /*!< DDRPHYC APB interface reset */ +#define RCC_DDRITFCR_DPHYRST_Pos (18U) +#define RCC_DDRITFCR_DPHYRST_Msk (0x1U << RCC_DDRITFCR_DPHYRST_Pos) /*!< 0x00040000 */ +#define RCC_DDRITFCR_DPHYRST RCC_DDRITFCR_DPHYRST_Msk /*!< DDRPHYC reset */ +#define RCC_DDRITFCR_DPHYCTLRST_Pos (19U) +#define RCC_DDRITFCR_DPHYCTLRST_Msk (0x1U << RCC_DDRITFCR_DPHYCTLRST_Pos) /*!< 0x00080000 */ +#define RCC_DDRITFCR_DPHYCTLRST RCC_DDRITFCR_DPHYCTLRST_Msk /*!< DDRPHYC Control reset */ +#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) +#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ +#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*!< RCC mode for DDR clock control */ +#define RCC_DDRITFCR_DDRCKMOD_0 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ +#define RCC_DDRITFCR_DDRCKMOD_1 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ +#define RCC_DDRITFCR_DDRCKMOD_2 (0x4U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00400000 */ +#define RCC_DDRITFCR_GSKPMOD_Pos (23U) +#define RCC_DDRITFCR_GSKPMOD_Msk (0x1U << RCC_DDRITFCR_GSKPMOD_Pos) /*!< 0x00800000 */ +#define RCC_DDRITFCR_GSKPMOD RCC_DDRITFCR_GSKPMOD_Msk /*!< Glitch Skipper (GSKP) Mode */ +#define RCC_DDRITFCR_GSKPCTRL_Pos (24U) +#define RCC_DDRITFCR_GSKPCTRL_Msk (0x1U << RCC_DDRITFCR_GSKPCTRL_Pos) /*!< 0x01000000 */ +#define RCC_DDRITFCR_GSKPCTRL RCC_DDRITFCR_GSKPCTRL_Msk /*!< Glitch Skipper (GSKP) control */ +#define RCC_DDRITFCR_DFILP_WIDTH_Pos (25U) +#define RCC_DDRITFCR_DFILP_WIDTH_Msk (0x7U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x0E000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH RCC_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command */ +#define RCC_DDRITFCR_DFILP_WIDTH_0 (0x1U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x02000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_1 (0x2U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x04000000 */ +#define RCC_DDRITFCR_DFILP_WIDTH_2 (0x4U << RCC_DDRITFCR_DFILP_WIDTH_Pos) /*!< 0x08000000 */ +#define RCC_DDRITFCR_GSKP_DUR_Pos (28U) +#define RCC_DDRITFCR_GSKP_DUR_Msk (0xFU << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0xF0000000 */ +#define RCC_DDRITFCR_GSKP_DUR RCC_DDRITFCR_GSKP_DUR_Msk /*!< Glitch skipper duration in automatic mode */ +#define RCC_DDRITFCR_GSKP_DUR_0 (0x1U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x10000000 */ +#define RCC_DDRITFCR_GSKP_DUR_1 (0x2U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x20000000 */ +#define RCC_DDRITFCR_GSKP_DUR_2 (0x4U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x40000000 */ +#define RCC_DDRITFCR_GSKP_DUR_3 (0x8U << RCC_DDRITFCR_GSKP_DUR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for RCC_MP_BOOTCR register *****************/ +#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) +#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*!< MCU Boot Enable after Standby */ +#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) +#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*!< MPU Boot Enable after Standby */ + +/*************** Bit definition for RCC_MP_SREQSETR register ****************/ +#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/*************** Bit definition for RCC_MP_SREQCLRR register ****************/ +#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) +#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ +#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*!< Stop Request for MPU processor number 0 */ +#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) +#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ +#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*!< Stop Request for MPU processor number 1 */ + +/****************** Bit definition for RCC_MP_GCR register ******************/ +#define RCC_MP_GCR_BOOT_MCU_Pos (0U) +#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ +#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*!< Allows the MCU to boot */ + +/**************** Bit definition for RCC_MP_APRSTCR register ****************/ +#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) +#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*!< Reset Delay Control Enable */ +#define RCC_MP_APRSTCR_RSTTO_Pos (8U) +#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*!< Reset Timeout Delay Adjust */ +#define RCC_MP_APRSTCR_RSTTO_0 (0x1U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTCR_RSTTO_1 (0x2U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTCR_RSTTO_2 (0x4U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTCR_RSTTO_3 (0x8U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTCR_RSTTO_4 (0x10U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTCR_RSTTO_5 (0x20U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTCR_RSTTO_6 (0x40U << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00004000 */ + +/**************** Bit definition for RCC_MP_APRSTSR register ****************/ +#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) +#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ +#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*!< Reset Timeout Delay Value */ +#define RCC_MP_APRSTSR_RSTTOV_0 (0x1U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000100 */ +#define RCC_MP_APRSTSR_RSTTOV_1 (0x2U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000200 */ +#define RCC_MP_APRSTSR_RSTTOV_2 (0x4U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000400 */ +#define RCC_MP_APRSTSR_RSTTOV_3 (0x8U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00000800 */ +#define RCC_MP_APRSTSR_RSTTOV_4 (0x10U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00001000 */ +#define RCC_MP_APRSTSR_RSTTOV_5 (0x20U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00002000 */ +#define RCC_MP_APRSTSR_RSTTOV_6 (0x40U << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00004000 */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< LSE oscillator enabled */ +#define RCC_BDCR_LSEBYP_Pos (1U) +#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< LSE oscillator bypass */ +#define RCC_BDCR_LSERDY_Pos (2U) +#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< LSE oscillator ready */ +#define RCC_BDCR_DIGBYP_Pos (3U) +#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*!< LSE digital bypass */ +#define RCC_BDCR_LSEDRV_Pos (4U) +#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSE oscillator driving capability */ +#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON_Pos (8U) +#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*!< LSE clock security system enable */ +#define RCC_BDCR_LSECSSD_Pos (9U) +#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*!< LSE clock security system failure detection */ +#define RCC_BDCR_RTCSRC_Pos (16U) +#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ +#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /*!< RTC clock source selection */ +#define RCC_BDCR_RTCSRC_0 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_RTCSRC_1 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ +#define RCC_BDCR_RTCCKEN_Pos (20U) +#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ +#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_VSWRST_Pos (31U) +#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< V Switch domain software reset */ + +/***************** Bit definition for RCC_RDLSICR register ******************/ +#define RCC_RDLSICR_LSION_Pos (0U) +#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*!< LSI oscillator enabled */ +#define RCC_RDLSICR_LSIRDY_Pos (1U) +#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*!< LSI oscillator ready */ +#define RCC_RDLSICR_MRD_Pos (16U) +#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ +#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*!< Minimum Reset Duration */ +#define RCC_RDLSICR_MRD_0 (0x1U << RCC_RDLSICR_MRD_Pos) /*!< 0x00010000 */ +#define RCC_RDLSICR_MRD_1 (0x2U << RCC_RDLSICR_MRD_Pos) /*!< 0x00020000 */ +#define RCC_RDLSICR_MRD_2 (0x4U << RCC_RDLSICR_MRD_Pos) /*!< 0x00040000 */ +#define RCC_RDLSICR_MRD_3 (0x8U << RCC_RDLSICR_MRD_Pos) /*!< 0x00080000 */ +#define RCC_RDLSICR_MRD_4 (0x10U << RCC_RDLSICR_MRD_Pos) /*!< 0x00100000 */ +#define RCC_RDLSICR_EADLY_Pos (24U) +#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ +#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*!< External access delays */ +#define RCC_RDLSICR_EADLY_0 (0x1U << RCC_RDLSICR_EADLY_Pos) /*!< 0x01000000 */ +#define RCC_RDLSICR_EADLY_1 (0x2U << RCC_RDLSICR_EADLY_Pos) /*!< 0x02000000 */ +#define RCC_RDLSICR_EADLY_2 (0x4U << RCC_RDLSICR_EADLY_Pos) /*!< 0x04000000 */ +#define RCC_RDLSICR_SPARE_Pos (27U) +#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ +#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*!< Spare bits */ +#define RCC_RDLSICR_SPARE_0 (0x1U << RCC_RDLSICR_SPARE_Pos) /*!< 0x08000000 */ +#define RCC_RDLSICR_SPARE_1 (0x2U << RCC_RDLSICR_SPARE_Pos) /*!< 0x10000000 */ +#define RCC_RDLSICR_SPARE_2 (0x4U << RCC_RDLSICR_SPARE_Pos) /*!< 0x20000000 */ +#define RCC_RDLSICR_SPARE_3 (0x8U << RCC_RDLSICR_SPARE_Pos) /*!< 0x40000000 */ +#define RCC_RDLSICR_SPARE_4 (0x10U << RCC_RDLSICR_SPARE_Pos) /*!< 0x80000000 */ + +/*************** Bit definition for RCC_APB4RSTSETR register ****************/ +#define RCC_APB4RSTSETR_LTDCRST_Pos (0U) +#define RCC_APB4RSTSETR_LTDCRST_Msk (0x1U << RCC_APB4RSTSETR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTSETR_LTDCRST RCC_APB4RSTSETR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTSETR_DSIRST_Pos (4U) +#define RCC_APB4RSTSETR_DSIRST_Msk (0x1U << RCC_APB4RSTSETR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTSETR_DSIRST RCC_APB4RSTSETR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTSETR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTSETR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTSETR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTSETR_DDRPERFMRST RCC_APB4RSTSETR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTSETR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTSETR_USBPHYRST_Msk (0x1U << RCC_APB4RSTSETR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTSETR_USBPHYRST RCC_APB4RSTSETR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB4RSTCLRR register ****************/ +#define RCC_APB4RSTCLRR_LTDCRST_Pos (0U) +#define RCC_APB4RSTCLRR_LTDCRST_Msk (0x1U << RCC_APB4RSTCLRR_LTDCRST_Pos) /*!< 0x00000001 */ +#define RCC_APB4RSTCLRR_LTDCRST RCC_APB4RSTCLRR_LTDCRST_Msk /*!< LTDC block reset */ +#define RCC_APB4RSTCLRR_DSIRST_Pos (4U) +#define RCC_APB4RSTCLRR_DSIRST_Msk (0x1U << RCC_APB4RSTCLRR_DSIRST_Pos) /*!< 0x00000010 */ +#define RCC_APB4RSTCLRR_DSIRST RCC_APB4RSTCLRR_DSIRST_Msk /*!< DSI block reset */ +#define RCC_APB4RSTCLRR_DDRPERFMRST_Pos (8U) +#define RCC_APB4RSTCLRR_DDRPERFMRST_Msk (0x1U << RCC_APB4RSTCLRR_DDRPERFMRST_Pos) /*!< 0x00000100 */ +#define RCC_APB4RSTCLRR_DDRPERFMRST RCC_APB4RSTCLRR_DDRPERFMRST_Msk /*!< DDRPERFM block reset */ +#define RCC_APB4RSTCLRR_USBPHYRST_Pos (16U) +#define RCC_APB4RSTCLRR_USBPHYRST_Msk (0x1U << RCC_APB4RSTCLRR_USBPHYRST_Pos) /*!< 0x00010000 */ +#define RCC_APB4RSTCLRR_USBPHYRST RCC_APB4RSTCLRR_USBPHYRST_Msk /*!< USBPHYC block reset */ + +/*************** Bit definition for RCC_APB5RSTSETR register ****************/ +#define RCC_APB5RSTSETR_SPI6RST_Pos (0U) +#define RCC_APB5RSTSETR_SPI6RST_Msk (0x1U << RCC_APB5RSTSETR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTSETR_SPI6RST RCC_APB5RSTSETR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTSETR_I2C4RST_Pos (2U) +#define RCC_APB5RSTSETR_I2C4RST_Msk (0x1U << RCC_APB5RSTSETR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTSETR_I2C4RST RCC_APB5RSTSETR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTSETR_I2C6RST_Pos (3U) +#define RCC_APB5RSTSETR_I2C6RST_Msk (0x1U << RCC_APB5RSTSETR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTSETR_I2C6RST RCC_APB5RSTSETR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTSETR_USART1RST_Pos (4U) +#define RCC_APB5RSTSETR_USART1RST_Msk (0x1U << RCC_APB5RSTSETR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTSETR_USART1RST RCC_APB5RSTSETR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTSETR_STGENRST_Pos (20U) +#define RCC_APB5RSTSETR_STGENRST_Msk (0x1U << RCC_APB5RSTSETR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTSETR_STGENRST RCC_APB5RSTSETR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_APB5RSTCLRR register ****************/ +#define RCC_APB5RSTCLRR_SPI6RST_Pos (0U) +#define RCC_APB5RSTCLRR_SPI6RST_Msk (0x1U << RCC_APB5RSTCLRR_SPI6RST_Pos) /*!< 0x00000001 */ +#define RCC_APB5RSTCLRR_SPI6RST RCC_APB5RSTCLRR_SPI6RST_Msk /*!< SPI6 block reset */ +#define RCC_APB5RSTCLRR_I2C4RST_Pos (2U) +#define RCC_APB5RSTCLRR_I2C4RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTCLRR_I2C4RST RCC_APB5RSTCLRR_I2C4RST_Msk /*!< I2C4 block reset */ +#define RCC_APB5RSTCLRR_I2C6RST_Pos (3U) +#define RCC_APB5RSTCLRR_I2C6RST_Msk (0x1U << RCC_APB5RSTCLRR_I2C6RST_Pos) /*!< 0x00000008 */ +#define RCC_APB5RSTCLRR_I2C6RST RCC_APB5RSTCLRR_I2C6RST_Msk /*!< I2C6 block reset */ +#define RCC_APB5RSTCLRR_USART1RST_Pos (4U) +#define RCC_APB5RSTCLRR_USART1RST_Msk (0x1U << RCC_APB5RSTCLRR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTCLRR_USART1RST RCC_APB5RSTCLRR_USART1RST_Msk /*!< USART1 block reset */ +#define RCC_APB5RSTCLRR_STGENRST_Pos (20U) +#define RCC_APB5RSTCLRR_STGENRST_Msk (0x1U << RCC_APB5RSTCLRR_STGENRST_Pos) /*!< 0x00100000 */ +#define RCC_APB5RSTCLRR_STGENRST RCC_APB5RSTCLRR_STGENRST_Msk /*!< STGEN block reset */ + +/*************** Bit definition for RCC_AHB5RSTSETR register ****************/ +#define RCC_AHB5RSTSETR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTSETR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTSETR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTSETR_GPIOZRST RCC_AHB5RSTSETR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTSETR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTSETR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTSETR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTSETR_CRYP1RST RCC_AHB5RSTSETR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTSETR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTSETR_HASH1RST_Msk (0x1U << RCC_AHB5RSTSETR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTSETR_HASH1RST RCC_AHB5RSTSETR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTSETR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTSETR_RNG1RST_Msk (0x1U << RCC_AHB5RSTSETR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTSETR_RNG1RST RCC_AHB5RSTSETR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTSETR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTSETR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTSETR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTSETR_AXIMCRST RCC_AHB5RSTSETR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB5RSTCLRR register ****************/ +#define RCC_AHB5RSTCLRR_GPIOZRST_Pos (0U) +#define RCC_AHB5RSTCLRR_GPIOZRST_Msk (0x1U << RCC_AHB5RSTCLRR_GPIOZRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTCLRR_GPIOZRST RCC_AHB5RSTCLRR_GPIOZRST_Msk /*!< GPIOZ secure block reset */ +#define RCC_AHB5RSTCLRR_CRYP1RST_Pos (4U) +#define RCC_AHB5RSTCLRR_CRYP1RST_Msk (0x1U << RCC_AHB5RSTCLRR_CRYP1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTCLRR_CRYP1RST RCC_AHB5RSTCLRR_CRYP1RST_Msk /*!< CRYP1 (3DES/AES1) block reset */ +#define RCC_AHB5RSTCLRR_HASH1RST_Pos (5U) +#define RCC_AHB5RSTCLRR_HASH1RST_Msk (0x1U << RCC_AHB5RSTCLRR_HASH1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTCLRR_HASH1RST RCC_AHB5RSTCLRR_HASH1RST_Msk /*!< HASH1 block reset */ +#define RCC_AHB5RSTCLRR_RNG1RST_Pos (6U) +#define RCC_AHB5RSTCLRR_RNG1RST_Msk (0x1U << RCC_AHB5RSTCLRR_RNG1RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB5RSTCLRR_RNG1RST RCC_AHB5RSTCLRR_RNG1RST_Msk /*!< RNG1 block reset */ +#define RCC_AHB5RSTCLRR_AXIMCRST_Pos (16U) +#define RCC_AHB5RSTCLRR_AXIMCRST_Msk (0x1U << RCC_AHB5RSTCLRR_AXIMCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB5RSTCLRR_AXIMCRST RCC_AHB5RSTCLRR_AXIMCRST_Msk /*!< AXIMC block reset */ + +/*************** Bit definition for RCC_AHB6RSTSETR register ****************/ +#define RCC_AHB6RSTSETR_GPURST_Pos (5U) +#define RCC_AHB6RSTSETR_GPURST_Msk (0x1U << RCC_AHB6RSTSETR_GPURST_Pos) /*!< 0x00000020 */ +#define RCC_AHB6RSTSETR_GPURST RCC_AHB6RSTSETR_GPURST_Msk /*!< GPU block reset */ +#define RCC_AHB6RSTSETR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTSETR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTSETR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTSETR_ETHMACRST RCC_AHB6RSTSETR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTSETR_FMCRST_Pos (12U) +#define RCC_AHB6RSTSETR_FMCRST_Msk (0x1U << RCC_AHB6RSTSETR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTSETR_FMCRST RCC_AHB6RSTSETR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTSETR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTSETR_QSPIRST_Msk (0x1U << RCC_AHB6RSTSETR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTSETR_QSPIRST RCC_AHB6RSTSETR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTSETR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTSETR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTSETR_SDMMC1RST RCC_AHB6RSTSETR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTSETR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTSETR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTSETR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTSETR_SDMMC2RST RCC_AHB6RSTSETR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTSETR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTSETR_CRC1RST_Msk (0x1U << RCC_AHB6RSTSETR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTSETR_CRC1RST RCC_AHB6RSTSETR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTSETR_USBHRST_Pos (24U) +#define RCC_AHB6RSTSETR_USBHRST_Msk (0x1U << RCC_AHB6RSTSETR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTSETR_USBHRST RCC_AHB6RSTSETR_USBHRST_Msk /*!< USBH block reset */ + +/*************** Bit definition for RCC_AHB6RSTCLRR register ****************/ +#define RCC_AHB6RSTCLRR_ETHMACRST_Pos (10U) +#define RCC_AHB6RSTCLRR_ETHMACRST_Msk (0x1U << RCC_AHB6RSTCLRR_ETHMACRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB6RSTCLRR_ETHMACRST RCC_AHB6RSTCLRR_ETHMACRST_Msk /*!< ETH block reset */ +#define RCC_AHB6RSTCLRR_FMCRST_Pos (12U) +#define RCC_AHB6RSTCLRR_FMCRST_Msk (0x1U << RCC_AHB6RSTCLRR_FMCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB6RSTCLRR_FMCRST RCC_AHB6RSTCLRR_FMCRST_Msk /*!< FMC block reset */ +#define RCC_AHB6RSTCLRR_QSPIRST_Pos (14U) +#define RCC_AHB6RSTCLRR_QSPIRST_Msk (0x1U << RCC_AHB6RSTCLRR_QSPIRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB6RSTCLRR_QSPIRST RCC_AHB6RSTCLRR_QSPIRST_Msk /*!< QUADSPI and the QUADSPI delay block reset */ +#define RCC_AHB6RSTCLRR_SDMMC1RST_Pos (16U) +#define RCC_AHB6RSTCLRR_SDMMC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC1RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB6RSTCLRR_SDMMC1RST RCC_AHB6RSTCLRR_SDMMC1RST_Msk /*!< SDMMC1 and the SDMMC1 delay (DLYBSD1) block reset */ +#define RCC_AHB6RSTCLRR_SDMMC2RST_Pos (17U) +#define RCC_AHB6RSTCLRR_SDMMC2RST_Msk (0x1U << RCC_AHB6RSTCLRR_SDMMC2RST_Pos) /*!< 0x00020000 */ +#define RCC_AHB6RSTCLRR_SDMMC2RST RCC_AHB6RSTCLRR_SDMMC2RST_Msk /*!< SDMMC2 and the SDMMC2 delay (DLYBSD2) block reset */ +#define RCC_AHB6RSTCLRR_CRC1RST_Pos (20U) +#define RCC_AHB6RSTCLRR_CRC1RST_Msk (0x1U << RCC_AHB6RSTCLRR_CRC1RST_Pos) /*!< 0x00100000 */ +#define RCC_AHB6RSTCLRR_CRC1RST RCC_AHB6RSTCLRR_CRC1RST_Msk /*!< CRC1 block reset */ +#define RCC_AHB6RSTCLRR_USBHRST_Pos (24U) +#define RCC_AHB6RSTCLRR_USBHRST_Msk (0x1U << RCC_AHB6RSTCLRR_USBHRST_Pos) /*!< 0x01000000 */ +#define RCC_AHB6RSTCLRR_USBHRST RCC_AHB6RSTCLRR_USBHRST_Msk /*!< USBH block reset */ + +/************** Bit definition for RCC_TZAHB6RSTSETR register ***************/ +#define RCC_TZAHB6RSTSETR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTSETR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTSETR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTSETR_MDMARST RCC_TZAHB6RSTSETR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_TZAHB6RSTCLRR register ***************/ +#define RCC_TZAHB6RSTCLRR_MDMARST_Pos (0U) +#define RCC_TZAHB6RSTCLRR_MDMARST_Msk (0x1U << RCC_TZAHB6RSTCLRR_MDMARST_Pos) /*!< 0x00000001 */ +#define RCC_TZAHB6RSTCLRR_MDMARST RCC_TZAHB6RSTCLRR_MDMARST_Msk /*!< MDMA block reset */ + +/************** Bit definition for RCC_MP_APB4ENSETR register ***************/ +#define RCC_MP_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENSETR_LTDCEN RCC_MP_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MP_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENSETR_DSIEN RCC_MP_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENSETR_DDRPERFMEN RCC_MP_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENSETR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENSETR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENSETR_IWDG2APBEN RCC_MP_APB4ENSETR_IWDG2APBEN_Msk /*!< IWDG2 APB clock enable */ +#define RCC_MP_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENSETR_USBPHYEN RCC_MP_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MP_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENSETR_STGENROEN RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB4ENCLRR register ***************/ +#define RCC_MP_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MP_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MP_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4ENCLRR_LTDCEN RCC_MP_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MP_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4ENCLRR_DSIEN RCC_MP_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MP_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4ENCLRR_DDRPERFMEN RCC_MP_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos (15U) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk (0x1U << RCC_MP_APB4ENCLRR_IWDG2APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4ENCLRR_IWDG2APBEN RCC_MP_APB4ENCLRR_IWDG2APBEN_Msk /*!< IWDG2 APB clock disable */ +#define RCC_MP_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MP_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MP_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4ENCLRR_USBPHYEN RCC_MP_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MP_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MP_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MP_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4ENCLRR_STGENROEN RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MP_APB5ENSETR register ***************/ +#define RCC_MP_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENSETR_SPI6EN RCC_MP_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENSETR_I2C4EN RCC_MP_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENSETR_I2C6EN RCC_MP_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MP_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENSETR_USART1EN RCC_MP_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENSETR_RTCAPBEN RCC_MP_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MP_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENSETR_TZC1EN RCC_MP_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MP_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENSETR_TZC2EN RCC_MP_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MP_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENSETR_TZPCEN RCC_MP_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENSETR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENSETR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENSETR_IWDG1APBEN RCC_MP_APB5ENSETR_IWDG1APBEN_Msk /*!< IWDG1 APB clock enable */ +#define RCC_MP_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MP_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENSETR_BSECEN RCC_MP_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MP_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MP_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENSETR_STGENEN RCC_MP_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB5ENCLRR register ***************/ +#define RCC_MP_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MP_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5ENCLRR_SPI6EN RCC_MP_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MP_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5ENCLRR_I2C4EN RCC_MP_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MP_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MP_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5ENCLRR_I2C6EN RCC_MP_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MP_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5ENCLRR_USART1EN RCC_MP_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MP_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN RCC_MP_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MP_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MP_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5ENCLRR_TZC1EN RCC_MP_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MP_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5ENCLRR_TZC2EN RCC_MP_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MP_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MP_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MP_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5ENCLRR_TZPCEN RCC_MP_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos (15U) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk (0x1U << RCC_MP_APB5ENCLRR_IWDG1APBEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5ENCLRR_IWDG1APBEN RCC_MP_APB5ENCLRR_IWDG1APBEN_Msk /*!< IWDG1 APB clock disable */ +#define RCC_MP_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MP_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MP_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5ENCLRR_BSECEN RCC_MP_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MP_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MP_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MP_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5ENCLRR_STGENEN RCC_MP_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MP_AHB5ENSETR register ***************/ +#define RCC_MP_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENSETR_GPIOZEN RCC_MP_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENSETR_CRYP1EN RCC_MP_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENSETR_HASH1EN RCC_MP_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENSETR_RNG1EN RCC_MP_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENSETR_BKPSRAMEN RCC_MP_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENSETR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENSETR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENSETR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENSETR_AXIMCEN RCC_MP_AHB5ENSETR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB5ENCLRR register ***************/ +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MP_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN RCC_MP_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MP_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5ENCLRR_CRYP1EN RCC_MP_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MP_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5ENCLRR_HASH1EN RCC_MP_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MP_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MP_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5ENCLRR_RNG1EN RCC_MP_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN RCC_MP_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Pos (16U) +#define RCC_MP_AHB5ENCLRR_AXIMCEN_Msk (0x1U << RCC_MP_AHB5ENCLRR_AXIMCEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB5ENCLRR_AXIMCEN RCC_MP_AHB5ENCLRR_AXIMCEN_Msk /*!< AXIMC clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENSETR register ***************/ +#define RCC_MP_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENSETR_MDMAEN RCC_MP_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENSETR_GPUEN RCC_MP_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENSETR_ETHCKEN RCC_MP_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENSETR_ETHTXEN RCC_MP_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENSETR_ETHRXEN RCC_MP_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MP_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENSETR_ETHMACEN RCC_MP_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MP_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENSETR_FMCEN RCC_MP_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENSETR_QSPIEN RCC_MP_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENSETR_SDMMC1EN RCC_MP_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENSETR_SDMMC2EN RCC_MP_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENSETR_CRC1EN RCC_MP_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENSETR_USBHEN RCC_MP_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB6ENCLRR register ***************/ +#define RCC_MP_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6ENCLRR_MDMAEN RCC_MP_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MP_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6ENCLRR_GPUEN RCC_MP_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MP_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6ENCLRR_ETHCKEN RCC_MP_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MP_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6ENCLRR_ETHTXEN RCC_MP_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MP_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6ENCLRR_ETHRXEN RCC_MP_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MP_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6ENCLRR_ETHMACEN RCC_MP_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MP_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MP_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6ENCLRR_FMCEN RCC_MP_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MP_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6ENCLRR_QSPIEN RCC_MP_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC1EN RCC_MP_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6ENCLRR_SDMMC2EN RCC_MP_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MP_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MP_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6ENCLRR_CRC1EN RCC_MP_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MP_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MP_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MP_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6ENCLRR_USBHEN RCC_MP_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENSETR register **************/ +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN RCC_MP_TZAHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************* Bit definition for RCC_MP_TZAHB6ENCLRR register **************/ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MP_TZAHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN RCC_MP_TZAHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENSETR register ***************/ +#define RCC_MC_APB4ENSETR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENSETR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENSETR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENSETR_LTDCEN RCC_MC_APB4ENSETR_LTDCEN_Msk /*!< LTDC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENSETR_DSIEN_Msk (0x1U << RCC_MC_APB4ENSETR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENSETR_DSIEN RCC_MC_APB4ENSETR_DSIEN_Msk /*!< DSI peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENSETR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENSETR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENSETR_DDRPERFMEN RCC_MC_APB4ENSETR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENSETR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENSETR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENSETR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENSETR_USBPHYEN RCC_MC_APB4ENSETR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks enable */ +#define RCC_MC_APB4ENSETR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENSETR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENSETR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENSETR_STGENROEN RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB4ENCLRR register ***************/ +#define RCC_MC_APB4ENCLRR_LTDCEN_Pos (0U) +#define RCC_MC_APB4ENCLRR_LTDCEN_Msk (0x1U << RCC_MC_APB4ENCLRR_LTDCEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4ENCLRR_LTDCEN RCC_MC_APB4ENCLRR_LTDCEN_Msk /*!< LTDC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DSIEN_Pos (4U) +#define RCC_MC_APB4ENCLRR_DSIEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DSIEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4ENCLRR_DSIEN RCC_MC_APB4ENCLRR_DSIEN_Msk /*!< DSI peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos (8U) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk (0x1U << RCC_MC_APB4ENCLRR_DDRPERFMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4ENCLRR_DDRPERFMEN RCC_MC_APB4ENCLRR_DDRPERFMEN_Msk /*!< DDRPERFM APB clock enable */ +#define RCC_MC_APB4ENCLRR_USBPHYEN_Pos (16U) +#define RCC_MC_APB4ENCLRR_USBPHYEN_Msk (0x1U << RCC_MC_APB4ENCLRR_USBPHYEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4ENCLRR_USBPHYEN RCC_MC_APB4ENCLRR_USBPHYEN_Msk /*!< USBPHYC peripheral clocks disable */ +#define RCC_MC_APB4ENCLRR_STGENROEN_Pos (20U) +#define RCC_MC_APB4ENCLRR_STGENROEN_Msk (0x1U << RCC_MC_APB4ENCLRR_STGENROEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4ENCLRR_STGENROEN RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface peripheral clocks disable */ + +/************** Bit definition for RCC_MC_APB5ENSETR register ***************/ +#define RCC_MC_APB5ENSETR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENSETR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENSETR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENSETR_SPI6EN RCC_MC_APB5ENSETR_SPI6EN_Msk /*!< SPI6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENSETR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENSETR_I2C4EN RCC_MC_APB5ENSETR_I2C4EN_Msk /*!< I2C4 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENSETR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENSETR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENSETR_I2C6EN RCC_MC_APB5ENSETR_I2C6EN_Msk /*!< I2C6 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENSETR_USART1EN_Msk (0x1U << RCC_MC_APB5ENSETR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENSETR_USART1EN RCC_MC_APB5ENSETR_USART1EN_Msk /*!< USART1 peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENSETR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENSETR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENSETR_RTCAPBEN RCC_MC_APB5ENSETR_RTCAPBEN_Msk /*!< RTC APB clock enable */ +#define RCC_MC_APB5ENSETR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENSETR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENSETR_TZC1EN RCC_MC_APB5ENSETR_TZC1EN_Msk /*!< TZC AXI port 1 clocks enable */ +#define RCC_MC_APB5ENSETR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENSETR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENSETR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENSETR_TZC2EN RCC_MC_APB5ENSETR_TZC2EN_Msk /*!< TZC AXI port 2 clocks enable */ +#define RCC_MC_APB5ENSETR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENSETR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENSETR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENSETR_TZPCEN RCC_MC_APB5ENSETR_TZPCEN_Msk /*!< TZPC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENSETR_BSECEN_Msk (0x1U << RCC_MC_APB5ENSETR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENSETR_BSECEN RCC_MC_APB5ENSETR_BSECEN_Msk /*!< BSEC peripheral clocks enable */ +#define RCC_MC_APB5ENSETR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENSETR_STGENEN_Msk (0x1U << RCC_MC_APB5ENSETR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENSETR_STGENEN RCC_MC_APB5ENSETR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB5ENCLRR register ***************/ +#define RCC_MC_APB5ENCLRR_SPI6EN_Pos (0U) +#define RCC_MC_APB5ENCLRR_SPI6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_SPI6EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5ENCLRR_SPI6EN RCC_MC_APB5ENCLRR_SPI6EN_Msk /*!< SPI6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C4EN_Pos (2U) +#define RCC_MC_APB5ENCLRR_I2C4EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5ENCLRR_I2C4EN RCC_MC_APB5ENCLRR_I2C4EN_Msk /*!< I2C4 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_I2C6EN_Pos (3U) +#define RCC_MC_APB5ENCLRR_I2C6EN_Msk (0x1U << RCC_MC_APB5ENCLRR_I2C6EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5ENCLRR_I2C6EN RCC_MC_APB5ENCLRR_I2C6EN_Msk /*!< I2C6 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_USART1EN_Pos (4U) +#define RCC_MC_APB5ENCLRR_USART1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5ENCLRR_USART1EN RCC_MC_APB5ENCLRR_USART1EN_Msk /*!< USART1 peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Pos (8U) +#define RCC_MC_APB5ENCLRR_RTCAPBEN_Msk (0x1U << RCC_MC_APB5ENCLRR_RTCAPBEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5ENCLRR_RTCAPBEN RCC_MC_APB5ENCLRR_RTCAPBEN_Msk /*!< RTC APB clock disable */ +#define RCC_MC_APB5ENCLRR_TZC1EN_Pos (11U) +#define RCC_MC_APB5ENCLRR_TZC1EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC1EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5ENCLRR_TZC1EN RCC_MC_APB5ENCLRR_TZC1EN_Msk /*!< TZC AXI port 1 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZC2EN_Pos (12U) +#define RCC_MC_APB5ENCLRR_TZC2EN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZC2EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5ENCLRR_TZC2EN RCC_MC_APB5ENCLRR_TZC2EN_Msk /*!< TZC AXI port 2 clocks disable */ +#define RCC_MC_APB5ENCLRR_TZPCEN_Pos (13U) +#define RCC_MC_APB5ENCLRR_TZPCEN_Msk (0x1U << RCC_MC_APB5ENCLRR_TZPCEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5ENCLRR_TZPCEN RCC_MC_APB5ENCLRR_TZPCEN_Msk /*!< TZPC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_BSECEN_Pos (16U) +#define RCC_MC_APB5ENCLRR_BSECEN_Msk (0x1U << RCC_MC_APB5ENCLRR_BSECEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5ENCLRR_BSECEN RCC_MC_APB5ENCLRR_BSECEN_Msk /*!< BSEC peripheral clocks disable */ +#define RCC_MC_APB5ENCLRR_STGENEN_Pos (20U) +#define RCC_MC_APB5ENCLRR_STGENEN_Msk (0x1U << RCC_MC_APB5ENCLRR_STGENEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5ENCLRR_STGENEN RCC_MC_APB5ENCLRR_STGENEN_Msk /*!< STGEN Controller part, peripheral clocks disable */ + +/************** Bit definition for RCC_MC_AHB5ENSETR register ***************/ +#define RCC_MC_AHB5ENSETR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENSETR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENSETR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENSETR_GPIOZEN RCC_MC_AHB5ENSETR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENSETR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENSETR_CRYP1EN RCC_MC_AHB5ENSETR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENSETR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENSETR_HASH1EN RCC_MC_AHB5ENSETR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENSETR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENSETR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENSETR_RNG1EN RCC_MC_AHB5ENSETR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENSETR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENSETR_BKPSRAMEN RCC_MC_AHB5ENSETR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB5ENCLRR register ***************/ +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Pos (0U) +#define RCC_MC_AHB5ENCLRR_GPIOZEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_GPIOZEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN RCC_MC_AHB5ENCLRR_GPIOZEN_Msk /*!< GPIOZ Secure peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Pos (4U) +#define RCC_MC_AHB5ENCLRR_CRYP1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_CRYP1EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5ENCLRR_CRYP1EN RCC_MC_AHB5ENCLRR_CRYP1EN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_HASH1EN_Pos (5U) +#define RCC_MC_AHB5ENCLRR_HASH1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_HASH1EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5ENCLRR_HASH1EN RCC_MC_AHB5ENCLRR_HASH1EN_Msk /*!< HASH1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_RNG1EN_Pos (6U) +#define RCC_MC_AHB5ENCLRR_RNG1EN_Msk (0x1U << RCC_MC_AHB5ENCLRR_RNG1EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5ENCLRR_RNG1EN RCC_MC_AHB5ENCLRR_RNG1EN_Msk /*!< RNG1 peripheral clocks enable */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos (8U) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk (0x1U << RCC_MC_AHB5ENCLRR_BKPSRAMEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN RCC_MC_AHB5ENCLRR_BKPSRAMEN_Msk /*!< BKPSRAM clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENSETR register ***************/ +#define RCC_MC_AHB6ENSETR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENSETR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENSETR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENSETR_MDMAEN RCC_MC_AHB6ENSETR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENSETR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENSETR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENSETR_GPUEN RCC_MC_AHB6ENSETR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENSETR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENSETR_ETHCKEN RCC_MC_AHB6ENSETR_ETHCKEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENSETR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENSETR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENSETR_ETHTXEN RCC_MC_AHB6ENSETR_ETHTXEN_Msk /*!< Ethernet Transmission Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENSETR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENSETR_ETHRXEN RCC_MC_AHB6ENSETR_ETHRXEN_Msk /*!< Ethernet Reception Clock Enable */ +#define RCC_MC_AHB6ENSETR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENSETR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENSETR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENSETR_ETHMACEN RCC_MC_AHB6ENSETR_ETHMACEN_Msk /*!< Ethernet MAC bus interface Clock Enable (hclk6 and aclk) */ +#define RCC_MC_AHB6ENSETR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENSETR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENSETR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENSETR_FMCEN RCC_MC_AHB6ENSETR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENSETR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENSETR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENSETR_QSPIEN RCC_MC_AHB6ENSETR_QSPIEN_Msk /*!< QUADSPI peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENSETR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENSETR_SDMMC1EN RCC_MC_AHB6ENSETR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENSETR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENSETR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENSETR_SDMMC2EN RCC_MC_AHB6ENSETR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENSETR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENSETR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENSETR_CRC1EN RCC_MC_AHB6ENSETR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENSETR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENSETR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENSETR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENSETR_USBHEN RCC_MC_AHB6ENSETR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB6ENCLRR register ***************/ +#define RCC_MC_AHB6ENCLRR_MDMAEN_Pos (0U) +#define RCC_MC_AHB6ENCLRR_MDMAEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_MDMAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6ENCLRR_MDMAEN RCC_MC_AHB6ENCLRR_MDMAEN_Msk /*!< MDMA peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_GPUEN_Pos (5U) +#define RCC_MC_AHB6ENCLRR_GPUEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_GPUEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6ENCLRR_GPUEN RCC_MC_AHB6ENCLRR_GPUEN_Msk /*!< GPU peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Pos (7U) +#define RCC_MC_AHB6ENCLRR_ETHCKEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHCKEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6ENCLRR_ETHCKEN RCC_MC_AHB6ENCLRR_ETHCKEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Pos (8U) +#define RCC_MC_AHB6ENCLRR_ETHTXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHTXEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6ENCLRR_ETHTXEN RCC_MC_AHB6ENCLRR_ETHTXEN_Msk /*!< Disable of the Ethernet Transmission Clock */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Pos (9U) +#define RCC_MC_AHB6ENCLRR_ETHRXEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHRXEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6ENCLRR_ETHRXEN RCC_MC_AHB6ENCLRR_ETHRXEN_Msk /*!< Disable of the Ethernet Reception Clock */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Pos (10U) +#define RCC_MC_AHB6ENCLRR_ETHMACEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_ETHMACEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6ENCLRR_ETHMACEN RCC_MC_AHB6ENCLRR_ETHMACEN_Msk /*!< Disable of the bus interface clock for ETH block (hclk6 and aclk) */ +#define RCC_MC_AHB6ENCLRR_FMCEN_Pos (12U) +#define RCC_MC_AHB6ENCLRR_FMCEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_FMCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6ENCLRR_FMCEN RCC_MC_AHB6ENCLRR_FMCEN_Msk /*!< FMC peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_QSPIEN_Pos (14U) +#define RCC_MC_AHB6ENCLRR_QSPIEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_QSPIEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6ENCLRR_QSPIEN RCC_MC_AHB6ENCLRR_QSPIEN_Msk /*!< QUADSPI and QUADSPI delay block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos (16U) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC1EN RCC_MC_AHB6ENCLRR_SDMMC1EN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos (17U) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_SDMMC2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6ENCLRR_SDMMC2EN RCC_MC_AHB6ENCLRR_SDMMC2EN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_CRC1EN_Pos (20U) +#define RCC_MC_AHB6ENCLRR_CRC1EN_Msk (0x1U << RCC_MC_AHB6ENCLRR_CRC1EN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6ENCLRR_CRC1EN RCC_MC_AHB6ENCLRR_CRC1EN_Msk /*!< CRC1 peripheral clocks enable */ +#define RCC_MC_AHB6ENCLRR_USBHEN_Pos (24U) +#define RCC_MC_AHB6ENCLRR_USBHEN_Msk (0x1U << RCC_MC_AHB6ENCLRR_USBHEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6ENCLRR_USBHEN RCC_MC_AHB6ENCLRR_USBHEN_Msk /*!< USBH peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB4LPENSETR register **************/ +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN RCC_MP_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENSETR_DSILPEN RCC_MP_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN RCC_MP_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN RCC_MP_APB4LPENSETR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENSETR_USBPHYLPEN RCC_MP_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENSETR_STGENROLPEN RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENSETR_STGENROSTPEN RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB4LPENCLRR register **************/ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN RCC_MP_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MP_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB4LPENCLRR_DSILPEN RCC_MP_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN RCC_MP_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos (15U) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN RCC_MP_APB4LPENCLRR_IWDG2APBLPEN_Msk /*!< IWDG2 APB clock enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN RCC_MP_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB4LPENCLRR_STGENROLPEN RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MP_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENSETR register **************/ +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN RCC_MP_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENSETR_I2C4LPEN RCC_MP_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENSETR_I2C6LPEN RCC_MP_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENSETR_USART1LPEN RCC_MP_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN RCC_MP_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENSETR_TZC1LPEN RCC_MP_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENSETR_TZC2LPEN RCC_MP_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENSETR_TZPCLPEN RCC_MP_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN RCC_MP_APB5LPENSETR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENSETR_BSECLPEN RCC_MP_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENSETR_STGENLPEN RCC_MP_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENSETR_STGENSTPEN RCC_MP_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_APB5LPENCLRR register **************/ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN RCC_MP_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB5LPENCLRR_I2C4LPEN RCC_MP_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB5LPENCLRR_I2C6LPEN RCC_MP_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MP_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB5LPENCLRR_USART1LPEN RCC_MP_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN RCC_MP_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB5LPENCLRR_TZC1LPEN RCC_MP_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB5LPENCLRR_TZC2LPEN RCC_MP_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB5LPENCLRR_TZPCLPEN RCC_MP_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos (15U) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN RCC_MP_APB5LPENCLRR_IWDG1APBLPEN_Msk /*!< IWDG1 APB clock enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MP_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB5LPENCLRR_BSECLPEN RCC_MP_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MP_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB5LPENCLRR_STGENLPEN RCC_MP_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MP_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB5LPENCLRR_STGENSTPEN RCC_MP_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MP_AHB5LPENSETR register **************/ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN RCC_MP_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN RCC_MP_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENSETR_HASH1LPEN RCC_MP_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENSETR_RNG1LPEN RCC_MP_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN RCC_MP_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB5LPENCLRR register **************/ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN RCC_MP_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN RCC_MP_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN RCC_MP_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN RCC_MP_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENSETR register **************/ +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN RCC_MP_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENSETR_GPULPEN RCC_MP_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN RCC_MP_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN RCC_MP_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN RCC_MP_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN RCC_MP_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENSETR_ETHSTPEN RCC_MP_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENSETR_FMCLPEN RCC_MP_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENSETR_QSPILPEN RCC_MP_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN RCC_MP_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN RCC_MP_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENSETR_CRC1LPEN RCC_MP_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENSETR_USBHLPEN RCC_MP_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB6LPENCLRR register **************/ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN RCC_MP_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MP_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB6LPENCLRR_GPULPEN RCC_MP_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN RCC_MP_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN RCC_MP_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN RCC_MP_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN RCC_MP_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN RCC_MP_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB6LPENCLRR_FMCLPEN RCC_MP_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_AHB6LPENCLRR_QSPILPEN RCC_MP_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN RCC_MP_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN RCC_MP_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN RCC_MP_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MP_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_AHB6LPENCLRR_USBHLPEN RCC_MP_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENSETR register *************/ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN RCC_MP_TZAHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************ Bit definition for RCC_MP_TZAHB6LPENCLRR register *************/ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN RCC_MP_TZAHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB4LPENSETR register **************/ +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENSETR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN RCC_MC_APB4LPENSETR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENSETR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENSETR_DSILPEN RCC_MC_APB4LPENSETR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN RCC_MC_APB4LPENSETR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENSETR_USBPHYLPEN RCC_MC_APB4LPENSETR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENSETR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENSETR_STGENROLPEN RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENSETR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENSETR_STGENROSTPEN RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB4LPENCLRR register **************/ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos (0U) +#define RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_LTDCLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN RCC_MC_APB4LPENCLRR_LTDCLPEN_Msk /*!< LTDC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DSILPEN_Pos (4U) +#define RCC_MC_APB4LPENCLRR_DSILPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DSILPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB4LPENCLRR_DSILPEN RCC_MC_APB4LPENCLRR_DSILPEN_Msk /*!< DSI peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos (8U) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN RCC_MC_APB4LPENCLRR_DDRPERFMLPEN_Msk /*!< DDRPERFM APB clock enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos (16U) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_USBPHYLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN RCC_MC_APB4LPENCLRR_USBPHYLPEN_Msk /*!< USBPHYC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos (20U) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB4LPENCLRR_STGENROLPEN RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos (21U) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk (0x1U << RCC_MC_APB4LPENCLRR_STGENROSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENSETR register **************/ +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENSETR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN RCC_MC_APB5LPENSETR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENSETR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENSETR_I2C4LPEN RCC_MC_APB5LPENSETR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENSETR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENSETR_I2C6LPEN RCC_MC_APB5LPENSETR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENSETR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENSETR_USART1LPEN RCC_MC_APB5LPENSETR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN RCC_MC_APB5LPENSETR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENSETR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENSETR_TZC1LPEN RCC_MC_APB5LPENSETR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENSETR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENSETR_TZC2LPEN RCC_MC_APB5LPENSETR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENSETR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENSETR_TZPCLPEN RCC_MC_APB5LPENSETR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENSETR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENSETR_BSECLPEN RCC_MC_APB5LPENSETR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENSETR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENSETR_STGENLPEN RCC_MC_APB5LPENSETR_STGENLPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENSETR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENSETR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENSETR_STGENSTPEN RCC_MC_APB5LPENSETR_STGENSTPEN_Msk /*!< STGEN Controller part, peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_APB5LPENCLRR register **************/ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos (0U) +#define RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_SPI6LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN RCC_MC_APB5LPENCLRR_SPI6LPEN_Msk /*!< SPI6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos (2U) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB5LPENCLRR_I2C4LPEN RCC_MC_APB5LPENCLRR_I2C4LPEN_Msk /*!< I2C4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos (3U) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_I2C6LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB5LPENCLRR_I2C6LPEN RCC_MC_APB5LPENCLRR_I2C6LPEN_Msk /*!< I2C6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Pos (4U) +#define RCC_MC_APB5LPENCLRR_USART1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB5LPENCLRR_USART1LPEN RCC_MC_APB5LPENCLRR_USART1LPEN_Msk /*!< USART1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos (8U) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN RCC_MC_APB5LPENCLRR_RTCAPBLPEN_Msk /*!< RTC APB clock enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos (11U) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC1LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB5LPENCLRR_TZC1LPEN RCC_MC_APB5LPENCLRR_TZC1LPEN_Msk /*!< TZC AXI port 1 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos (12U) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZC2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB5LPENCLRR_TZC2LPEN RCC_MC_APB5LPENCLRR_TZC2LPEN_Msk /*!< TZC AXI port 2 peripheral clocks disable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos (13U) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_TZPCLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB5LPENCLRR_TZPCLPEN RCC_MC_APB5LPENCLRR_TZPCLPEN_Msk /*!< TZPC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Pos (16U) +#define RCC_MC_APB5LPENCLRR_BSECLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_BSECLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB5LPENCLRR_BSECLPEN RCC_MC_APB5LPENCLRR_BSECLPEN_Msk /*!< BSEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Pos (20U) +#define RCC_MC_APB5LPENCLRR_STGENLPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB5LPENCLRR_STGENLPEN RCC_MC_APB5LPENCLRR_STGENLPEN_Msk /*!< STGEN peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos (21U) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk (0x1U << RCC_MC_APB5LPENCLRR_STGENSTPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB5LPENCLRR_STGENSTPEN RCC_MC_APB5LPENCLRR_STGENSTPEN_Msk /*!< STGEN peripheral clocks enable during CStop mode */ + +/************* Bit definition for RCC_MC_AHB5LPENSETR register **************/ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN RCC_MC_AHB5LPENSETR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN RCC_MC_AHB5LPENSETR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENSETR_HASH1LPEN RCC_MC_AHB5LPENSETR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENSETR_RNG1LPEN RCC_MC_AHB5LPENSETR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN RCC_MC_AHB5LPENSETR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB5LPENCLRR register **************/ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos (0U) +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN RCC_MC_AHB5LPENCLRR_GPIOZLPEN_Msk /*!< GPIOZ Secure peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos (4U) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN RCC_MC_AHB5LPENCLRR_CRYP1LPEN_Msk /*!< CRYP1 (3DES/AES1) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos (5U) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_HASH1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN RCC_MC_AHB5LPENCLRR_HASH1LPEN_Msk /*!< HASH1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos (6U) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_RNG1LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN RCC_MC_AHB5LPENCLRR_RNG1LPEN_Msk /*!< RNG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos (8U) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk (0x1U << RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN_Msk /*!< BKPSRAM clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENSETR register **************/ +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENSETR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN RCC_MC_AHB6LPENSETR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENSETR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENSETR_GPULPEN RCC_MC_AHB6LPENSETR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN RCC_MC_AHB6LPENSETR_ETHCKLPEN_Msk /*!< Enable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN RCC_MC_AHB6LPENSETR_ETHTXLPEN_Msk /*!< Enable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN RCC_MC_AHB6LPENSETR_ETHRXLPEN_Msk /*!< Enable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN RCC_MC_AHB6LPENSETR_ETHMACLPEN_Msk /*!< Enable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENSETR_ETHSTPEN RCC_MC_AHB6LPENSETR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENSETR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENSETR_FMCLPEN RCC_MC_AHB6LPENSETR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENSETR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENSETR_QSPILPEN RCC_MC_AHB6LPENSETR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN RCC_MC_AHB6LPENSETR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN RCC_MC_AHB6LPENSETR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENSETR_CRC1LPEN RCC_MC_AHB6LPENSETR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENSETR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENSETR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENSETR_USBHLPEN RCC_MC_AHB6LPENSETR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB6LPENCLRR register **************/ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos (0U) +#define RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_MDMALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN RCC_MC_AHB6LPENCLRR_MDMALPEN_Msk /*!< MDMA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Pos (5U) +#define RCC_MC_AHB6LPENCLRR_GPULPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_GPULPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB6LPENCLRR_GPULPEN RCC_MC_AHB6LPENCLRR_GPULPEN_Msk /*!< GPU peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos (7U) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN RCC_MC_AHB6LPENCLRR_ETHCKLPEN_Msk /*!< Disable of the Ethernet clock generated by the RCC (eth_ker_ck) during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos (8U) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN RCC_MC_AHB6LPENCLRR_ETHTXLPEN_Msk /*!< Disable of the Ethernet Transmission Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos (9U) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN RCC_MC_AHB6LPENCLRR_ETHRXLPEN_Msk /*!< Disable of the Ethernet Reception Clock during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos (10U) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN RCC_MC_AHB6LPENCLRR_ETHMACLPEN_Msk /*!< Disable of the bus interface clocks for ETH block during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos (11U) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_ETHSTPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN RCC_MC_AHB6LPENCLRR_ETHSTPEN_Msk /*!< ETH peripheral clock enable during CStop mode */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos (12U) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_FMCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB6LPENCLRR_FMCLPEN RCC_MC_AHB6LPENCLRR_FMCLPEN_Msk /*!< FMC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos (14U) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_QSPILPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_AHB6LPENCLRR_QSPILPEN RCC_MC_AHB6LPENCLRR_QSPILPEN_Msk /*!< QUADSPI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos (16U) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN RCC_MC_AHB6LPENCLRR_SDMMC1LPEN_Msk /*!< SDMMC1 and SDMMC1 delay (DLYBSD1) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos (17U) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN RCC_MC_AHB6LPENCLRR_SDMMC2LPEN_Msk /*!< SDMMC2 and SDMMC2 delay (DLYBSD2) block peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos (20U) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_CRC1LPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN RCC_MC_AHB6LPENCLRR_CRC1LPEN_Msk /*!< CRC1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos (24U) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk (0x1U << RCC_MC_AHB6LPENCLRR_USBHLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_AHB6LPENCLRR_USBHLPEN RCC_MC_AHB6LPENCLRR_USBHLPEN_Msk /*!< USBH peripheral clocks enable during CSleep mode */ + +/*************** Bit definition for RCC_BR_RSTSCLRR register ****************/ +#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ + +/*************** Bit definition for RCC_MP_GRSTCSETR register ***************/ +#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) +#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ +#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*!< System reset */ +#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) +#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ +#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*!< MCU reset */ +#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) +#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ +#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*!< MPU processor 0 reset */ +#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) +#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ +#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*!< MPU processor 1 reset */ + +/*************** Bit definition for RCC_MP_RSTSCLRR register ****************/ +#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) +#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*!< Spare bits */ + +/************** Bit definition for RCC_MP_IWDGFZSETR register ***************/ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 RCC_MP_IWDGFZSETR_FZ_IWDG1_Msk /*!< Freeze the IWDG1 clock */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZSETR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 RCC_MP_IWDGFZSETR_FZ_IWDG2_Msk /*!< Freeze the IWDG2 clock */ + +/************** Bit definition for RCC_MP_IWDGFZCLRR register ***************/ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos (0U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG1_Pos) /*!< 0x00000001 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 RCC_MP_IWDGFZCLRR_FZ_IWDG1_Msk /*!< Unfreeze the IWDG1 clock */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos (1U) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk (0x1U << RCC_MP_IWDGFZCLRR_FZ_IWDG2_Pos) /*!< 0x00000002 */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 RCC_MP_IWDGFZCLRR_FZ_IWDG2_Msk /*!< Unfreeze the IWDG2 clock */ + +/***************** Bit definition for RCC_MP_CIER register ******************/ +#define RCC_MP_CIER_LSIRDYIE_Pos (0U) +#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MP_CIER_LSERDYIE_Pos (1U) +#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MP_CIER_HSIRDYIE_Pos (2U) +#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MP_CIER_HSERDYIE_Pos (3U) +#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MP_CIER_CSIRDYIE_Pos (4U) +#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MP_CIER_PLL1DYIE_Pos (8U) +#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL2DYIE_Pos (9U) +#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL3DYIE_Pos (10U) +#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MP_CIER_PLL4DYIE_Pos (11U) +#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MP_CIER_LSECSSIE_Pos (16U) +#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MP_CIER_WKUPIE_Pos (20U) +#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MP_CIFR register ******************/ +#define RCC_MP_CIFR_LSIRDYF_Pos (0U) +#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MP_CIFR_LSERDYF_Pos (1U) +#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MP_CIFR_HSIRDYF_Pos (2U) +#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MP_CIFR_HSERDYF_Pos (3U) +#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MP_CIFR_CSIRDYF_Pos (4U) +#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL1DYF_Pos (8U) +#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL2DYF_Pos (9U) +#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL3DYF_Pos (10U) +#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MP_CIFR_PLL4DYF_Pos (11U) +#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MP_CIFR_LSECSSF_Pos (16U) +#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MP_CIFR_WKUPF_Pos (20U) +#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/**************** Bit definition for RCC_PWRLPDLYCR register ****************/ +#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) +#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ +#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*!< PWRLP_TEMPO value */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x1U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x2U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000002 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_2 (0x4U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000004 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_3 (0x8U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000008 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_4 (0x10U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000010 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_5 (0x20U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000020 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_6 (0x40U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000040 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_7 (0x80U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000080 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_8 (0x100U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000100 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_9 (0x200U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000200 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_10 (0x400U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000400 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_11 (0x800U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000800 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_12 (0x1000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00001000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_13 (0x2000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00002000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_14 (0x4000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00004000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_15 (0x8000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00008000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_16 (0x10000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00010000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_17 (0x20000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00020000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_18 (0x40000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00040000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_19 (0x80000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00080000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_20 (0x100000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00100000 */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_21 (0x200000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00200000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP_Pos (24U) +#define RCC_PWRLPDLYCR_MCTMPSKP_Msk (0x1U << RCC_PWRLPDLYCR_MCTMPSKP_Pos) /*!< 0x01000000 */ +#define RCC_PWRLPDLYCR_MCTMPSKP RCC_PWRLPDLYCR_MCTMPSKP_Msk /*!< Skip the PWR_DLY for MCU */ + +/*************** Bit definition for RCC_MP_RSTSSETR register ****************/ +#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) +#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) +#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) +#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) +#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) +#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) +#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) +#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) +#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) +#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) +#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ +#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*!< System Standby reset flag */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) +#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ +#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*!< MPU CStandby reset flag */ +#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) +#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ +#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*!< MPU processor 0 reset flag */ +#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) +#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ +#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*!< MPU processor 1 reset flag */ +#define RCC_MP_RSTSSETR_SPARE_Pos (15U) +#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ +#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*!< Spare bits */ + +/***************** Bit definition for RCC_MCO1CFGR register *****************/ +#define RCC_MCO1CFGR_MCO1SEL_Pos (0U) +#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*!< MCO1 clock output selection */ +#define RCC_MCO1CFGR_MCO1SEL_0 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO1CFGR_MCO1SEL_1 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO1CFGR_MCO1SEL_2 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO1CFGR_MCO1DIV_Pos (4U) +#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*!< MCO1 prescaler */ +#define RCC_MCO1CFGR_MCO1DIV_0 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO1CFGR_MCO1DIV_1 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO1CFGR_MCO1DIV_2 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO1CFGR_MCO1DIV_3 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO1CFGR_MCO1ON_Pos (12U) +#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*!< Control of the MCO1 output */ + +/***************** Bit definition for RCC_MCO2CFGR register *****************/ +#define RCC_MCO2CFGR_MCO2SEL_Pos (0U) +#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */ +#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock output 2 */ +#define RCC_MCO2CFGR_MCO2SEL_0 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */ +#define RCC_MCO2CFGR_MCO2SEL_1 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */ +#define RCC_MCO2CFGR_MCO2SEL_2 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */ +#define RCC_MCO2CFGR_MCO2DIV_Pos (4U) +#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */ +#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*!< MCO2 prescaler */ +#define RCC_MCO2CFGR_MCO2DIV_0 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */ +#define RCC_MCO2CFGR_MCO2DIV_1 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */ +#define RCC_MCO2CFGR_MCO2DIV_2 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */ +#define RCC_MCO2CFGR_MCO2DIV_3 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */ +#define RCC_MCO2CFGR_MCO2ON_Pos (12U) +#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */ +#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*!< Control of the MCO2 output */ + +/****************** Bit definition for RCC_OCRDYR register ******************/ +#define RCC_OCRDYR_HSIRDY_Pos (0U) +#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */ +#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*!< HSI clock ready flag */ +#define RCC_OCRDYR_HSIDIVRDY_Pos (2U) +#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */ +#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*!< HSI divider ready flag */ +#define RCC_OCRDYR_CSIRDY_Pos (4U) +#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */ +#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*!< CSI clock ready flag */ +#define RCC_OCRDYR_HSERDY_Pos (8U) +#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */ +#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*!< HSE clock ready flag */ +#define RCC_OCRDYR_MPUCKRDY_Pos (23U) +#define RCC_OCRDYR_MPUCKRDY_Msk (0x1U << RCC_OCRDYR_MPUCKRDY_Pos) /*!< 0x00800000 */ +#define RCC_OCRDYR_MPUCKRDY RCC_OCRDYR_MPUCKRDY_Msk /*!< MPU clock ready flag */ +#define RCC_OCRDYR_AXICKRDY_Pos (24U) +#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */ +#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready flag */ +#define RCC_OCRDYR_CKREST_Pos (25U) +#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */ +#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*!< Clock Restore State Machine Status */ + +/***************** Bit definition for RCC_DBGCFGR register ******************/ +#define RCC_DBGCFGR_TRACEDIV_Pos (0U) +#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */ +#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*!< Clock divider for the trace clock (ck_trace) */ +#define RCC_DBGCFGR_TRACEDIV_0 (0x1U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000001 */ +#define RCC_DBGCFGR_TRACEDIV_1 (0x2U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000002 */ +#define RCC_DBGCFGR_TRACEDIV_2 (0x4U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000004 */ +#define RCC_DBGCFGR_DBGCKEN_Pos (8U) +#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */ +#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*!< Clock enable for debug function */ +#define RCC_DBGCFGR_TRACECKEN_Pos (9U) +#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */ +#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*!< Clock enable for trace function */ +#define RCC_DBGCFGR_DBGRST_Pos (12U) +#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */ +#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*!< Reset of the debug function */ + +/***************** Bit definition for RCC_RCK3SELR register *****************/ +#define RCC_RCK3SELR_PLL3SRC_Pos (0U) +#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*!< Reference clock selection for PLL3 */ +#define RCC_RCK3SELR_PLL3SRC_0 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK3SELR_PLL3SRC_1 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U) +#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*!< PLL3 reference clock switch status */ + +/***************** Bit definition for RCC_RCK4SELR register *****************/ +#define RCC_RCK4SELR_PLL4SRC_Pos (0U) +#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */ +#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*!< Reference clock selection for PLL4 */ +#define RCC_RCK4SELR_PLL4SRC_0 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */ +#define RCC_RCK4SELR_PLL4SRC_1 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */ +#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U) +#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */ +#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*!< PLL4 reference clock switch status */ + +/**************** Bit definition for RCC_TIMG1PRER register *****************/ +#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U) +#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U) +#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*!< Timers clocks prescaler status */ + +/**************** Bit definition for RCC_TIMG2PRER register *****************/ +#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U) +#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */ +#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*!< Timers clocks prescaler selection */ +#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U) +#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */ +#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*!< Timers clocks prescaler status */ + +/***************** Bit definition for RCC_MCUDIVR register ******************/ +#define RCC_MCUDIVR_MCUDIV_Pos (0U) +#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */ +#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*!< MCU clock divider */ +#define RCC_MCUDIVR_MCUDIV_0 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */ +#define RCC_MCUDIVR_MCUDIV_1 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */ +#define RCC_MCUDIVR_MCUDIV_2 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */ +#define RCC_MCUDIVR_MCUDIV_3 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */ +#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U) +#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*!< MCU clock prescaler status */ + +/***************** Bit definition for RCC_APB1DIVR register *****************/ +#define RCC_APB1DIVR_APB1DIV_Pos (0U) +#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*!< APB1 clock divider */ +#define RCC_APB1DIVR_APB1DIV_0 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB1DIVR_APB1DIV_1 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB1DIVR_APB1DIV_2 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U) +#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*!< APB1 clock prescaler status */ + +/***************** Bit definition for RCC_APB2DIVR register *****************/ +#define RCC_APB2DIVR_APB2DIV_Pos (0U) +#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*!< APB2 clock divider */ +#define RCC_APB2DIVR_APB2DIV_0 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB2DIVR_APB2DIV_1 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB2DIVR_APB2DIV_2 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U) +#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*!< APB2 clock prescaler status */ + +/***************** Bit definition for RCC_APB3DIVR register *****************/ +#define RCC_APB3DIVR_APB3DIV_Pos (0U) +#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */ +#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*!< APB3 clock divider */ +#define RCC_APB3DIVR_APB3DIV_0 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */ +#define RCC_APB3DIVR_APB3DIV_1 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */ +#define RCC_APB3DIVR_APB3DIV_2 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */ +#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U) +#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */ +#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*!< APB3 clock prescaler status */ + +/****************** Bit definition for RCC_PLL3CR register ******************/ +#define RCC_PLL3CR_PLLON_Pos (0U) +#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*!< PLL3 enable */ +#define RCC_PLL3CR_PLL3RDY_Pos (1U) +#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ +#define RCC_PLL3CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*!< Clock Spreading Generator of PLL3 enable */ +#define RCC_PLL3CR_DIVPEN_Pos (4U) +#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLL3CR_DIVQEN_Pos (5U) +#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLL3CR_DIVREN_Pos (6U) +#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*!< PLL3 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL3CFGR1 register *****************/ +#define RCC_PLL3CFGR1_DIVN_Pos (0U) +#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*!< Multiplication factor for PLL3 VCO */ +#define RCC_PLL3CFGR1_DIVN_0 (0x1U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR1_DIVN_1 (0x2U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR1_DIVN_2 (0x4U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR1_DIVN_3 (0x8U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR1_DIVN_4 (0x10U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR1_DIVN_5 (0x20U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR1_DIVN_6 (0x40U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR1_DIVN_7 (0x80U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3CFGR1_DIVN_8 (0x100U << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR1_DIVM3_Pos (16U) +#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */ +#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*!< Prescaler for PLL3 */ +#define RCC_PLL3CFGR1_DIVM3_0 (0x1U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR1_DIVM3_1 (0x2U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR1_DIVM3_2 (0x4U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR1_DIVM3_3 (0x8U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR1_DIVM3_4 (0x10U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR1_DIVM3_5 (0x20U << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR1_IFRGE_Pos (24U) +#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*!< PLL3 input frequency range */ +#define RCC_PLL3CFGR1_IFRGE_0 (0x1U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL3CFGR1_IFRGE_1 (0x2U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL3CFGR2 register *****************/ +#define RCC_PLL3CFGR2_DIVP_Pos (0U) +#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*!< PLL3 DIVP division factor */ +#define RCC_PLL3CFGR2_DIVP_0 (0x1U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL3CFGR2_DIVP_1 (0x2U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL3CFGR2_DIVP_2 (0x4U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL3CFGR2_DIVP_3 (0x8U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL3CFGR2_DIVP_4 (0x10U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL3CFGR2_DIVP_5 (0x20U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL3CFGR2_DIVP_6 (0x40U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL3CFGR2_DIVQ_Pos (8U) +#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*!< PLL3 DIVQ division factor */ +#define RCC_PLL3CFGR2_DIVQ_0 (0x1U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL3CFGR2_DIVQ_1 (0x2U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL3CFGR2_DIVQ_2 (0x4U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL3CFGR2_DIVQ_3 (0x8U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL3CFGR2_DIVQ_4 (0x10U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL3CFGR2_DIVQ_5 (0x20U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL3CFGR2_DIVQ_6 (0x40U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL3CFGR2_DIVR_Pos (16U) +#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*!< PLL3 DIVR division factor */ +#define RCC_PLL3CFGR2_DIVR_0 (0x1U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL3CFGR2_DIVR_1 (0x2U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL3CFGR2_DIVR_2 (0x4U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL3CFGR2_DIVR_3 (0x8U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL3CFGR2_DIVR_4 (0x10U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL3CFGR2_DIVR_5 (0x20U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL3CFGR2_DIVR_6 (0x40U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL3FRACR register *****************/ +#define RCC_PLL3FRACR_FRACV_Pos (3U) +#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL3 VCO */ +#define RCC_PLL3FRACR_FRACV_0 (0x1U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL3FRACR_FRACV_1 (0x2U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL3FRACR_FRACV_2 (0x4U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL3FRACR_FRACV_3 (0x8U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL3FRACR_FRACV_4 (0x10U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL3FRACR_FRACV_5 (0x20U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL3FRACR_FRACV_6 (0x40U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL3FRACR_FRACV_7 (0x80U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL3FRACR_FRACV_8 (0x100U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL3FRACR_FRACV_9 (0x200U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL3FRACR_FRACV_10 (0x400U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL3FRACR_FRACV_11 (0x800U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL3FRACR_FRACV_12 (0x1000U << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL3FRACR_FRACLE_Pos (16U) +#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*!< PLL3 fractional latch enable */ /******************** Bit definition for RCC_PLL3CSGR register********************/ #define RCC_PLL3CSGR_MOD_PER_Pos (0U) @@ -21946,85 +28322,110 @@ typedef struct #define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/ #define RCC_PLL3CSGR_INC_STEP_Pos (16U) #define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3CSGR_INC_STEP_Pos (16U) +#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/ -/******************** Bit definition for RCC_PLL4CR register********************/ -#define RCC_PLL4CR_PLLON_Pos (0U) -#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/ -#define RCC_PLL4CR_PLL4RDY_Pos (1U) -#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ -#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/ -#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) -#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ -#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ -#define RCC_PLL4CR_DIVPEN_Pos (4U) -#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ -#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/ -#define RCC_PLL4CR_DIVQEN_Pos (5U) -#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ -#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/ -#define RCC_PLL4CR_DIVREN_Pos (6U) -#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ -#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/ - -/******************** Bit definition for RCC_PLL4CFGR1 register********************/ -#define RCC_PLL4CFGR1_DIVN_Pos (0U) -#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ -#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/ -/* @note Valid division rations for DIVN: between 25 and 200 */ -#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */ -#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */ -#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */ - -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Pos (16U) -#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ -#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/ -/* @note "y" division factor must be an integer value between 1 and 64 */ -#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4)) - -#define RCC_PLL4CFGR1_IFRGE_Pos (24U) -#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ -#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/ -#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */ - /*between 4 and 8 MHz (default after reset) */ -#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is - between 8 and 16 MHz */ -/* @note other IFRGE values are reserved */ - -/******************** Bit definition for RCC_PLL4CFGR2 register********************/ -/* @TODO To compleate as needed */ -#define RCC_PLL4CFGR2_DIVP_Pos (0U) -#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ -#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/ -#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ -#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ - -#define RCC_PLL4CFGR2_DIVQ_Pos (8U) -#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ -#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/ -#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ -#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ - -#define RCC_PLL4CFGR2_DIVR_Pos (16U) -#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ -#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/ -#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */ -#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ -#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ - -/******************** Bit definition for RCC_PLL4FRACR register********************/ -#define RCC_PLL4FRACR_FRACV_Pos (3U) -#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ -#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/ -/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */ - -#define RCC_PLL4FRACR_FRACLE_Pos (16U) -#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ -#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/ +/****************** Bit definition for RCC_PLL4CR register ******************/ +#define RCC_PLL4CR_PLLON_Pos (0U) +#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*!< PLL4 enable */ +#define RCC_PLL4CR_PLL4RDY_Pos (1U) +#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*!< PLL4 clock ready flag */ +#define RCC_PLL4CR_SSCG_CTRL_Pos (2U) +#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/ +#define RCC_PLL4CR_DIVPEN_Pos (4U) +#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*!< PLL4 DIVP divider output enable */ +#define RCC_PLL4CR_DIVQEN_Pos (5U) +#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*!< PLL4 DIVQ divider output enable */ +#define RCC_PLL4CR_DIVREN_Pos (6U) +#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*!< PLL4 DIVR divider output enable */ + +/**************** Bit definition for RCC_PLL4CFGR1 register *****************/ +#define RCC_PLL4CFGR1_DIVN_Pos (0U) +#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*!< Multiplication factor for PLL4 VCO */ +#define RCC_PLL4CFGR1_DIVN_0 (0x1U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR1_DIVN_1 (0x2U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR1_DIVN_2 (0x4U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR1_DIVN_3 (0x8U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR1_DIVN_4 (0x10U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR1_DIVN_5 (0x20U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR1_DIVN_6 (0x40U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR1_DIVN_7 (0x80U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL4CFGR1_DIVN_8 (0x100U << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR1_DIVM4_Pos (16U) +#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */ +#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*!< Prescaler for PLL4 */ +#define RCC_PLL4CFGR1_DIVM4_0 (0x1U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR1_DIVM4_1 (0x2U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR1_DIVM4_2 (0x4U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR1_DIVM4_3 (0x8U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR1_DIVM4_4 (0x10U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR1_DIVM4_5 (0x20U << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR1_IFRGE_Pos (24U) +#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */ +#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*!< PLL4 input frequency range */ +#define RCC_PLL4CFGR1_IFRGE_0 (0x1U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x01000000 */ +#define RCC_PLL4CFGR1_IFRGE_1 (0x2U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x02000000 */ + +/**************** Bit definition for RCC_PLL4CFGR2 register *****************/ +#define RCC_PLL4CFGR2_DIVP_Pos (0U) +#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */ +#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*!< PLL4 DIVP division factor */ +#define RCC_PLL4CFGR2_DIVP_0 (0x1U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */ +#define RCC_PLL4CFGR2_DIVP_1 (0x2U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000002 */ +#define RCC_PLL4CFGR2_DIVP_2 (0x4U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000004 */ +#define RCC_PLL4CFGR2_DIVP_3 (0x8U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000008 */ +#define RCC_PLL4CFGR2_DIVP_4 (0x10U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000010 */ +#define RCC_PLL4CFGR2_DIVP_5 (0x20U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000020 */ +#define RCC_PLL4CFGR2_DIVP_6 (0x40U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000040 */ +#define RCC_PLL4CFGR2_DIVQ_Pos (8U) +#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */ +#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*!< PLL4 DIVQ division factor */ +#define RCC_PLL4CFGR2_DIVQ_0 (0x1U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */ +#define RCC_PLL4CFGR2_DIVQ_1 (0x2U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000200 */ +#define RCC_PLL4CFGR2_DIVQ_2 (0x4U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000400 */ +#define RCC_PLL4CFGR2_DIVQ_3 (0x8U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000800 */ +#define RCC_PLL4CFGR2_DIVQ_4 (0x10U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00001000 */ +#define RCC_PLL4CFGR2_DIVQ_5 (0x20U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00002000 */ +#define RCC_PLL4CFGR2_DIVQ_6 (0x40U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00004000 */ +#define RCC_PLL4CFGR2_DIVR_Pos (16U) +#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */ +#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*!< PLL4 DIVR division factor */ +#define RCC_PLL4CFGR2_DIVR_0 (0x1U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */ +#define RCC_PLL4CFGR2_DIVR_1 (0x2U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00020000 */ +#define RCC_PLL4CFGR2_DIVR_2 (0x4U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00040000 */ +#define RCC_PLL4CFGR2_DIVR_3 (0x8U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00080000 */ +#define RCC_PLL4CFGR2_DIVR_4 (0x10U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00100000 */ +#define RCC_PLL4CFGR2_DIVR_5 (0x20U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00200000 */ +#define RCC_PLL4CFGR2_DIVR_6 (0x40U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00400000 */ + +/**************** Bit definition for RCC_PLL4FRACR register *****************/ +#define RCC_PLL4FRACR_FRACV_Pos (3U) +#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*!< Fractional part of the multiplication factor for PLL4 VCO */ +#define RCC_PLL4FRACR_FRACV_0 (0x1U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000008 */ +#define RCC_PLL4FRACR_FRACV_1 (0x2U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000010 */ +#define RCC_PLL4FRACR_FRACV_2 (0x4U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000020 */ +#define RCC_PLL4FRACR_FRACV_3 (0x8U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000040 */ +#define RCC_PLL4FRACR_FRACV_4 (0x10U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000080 */ +#define RCC_PLL4FRACR_FRACV_5 (0x20U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000100 */ +#define RCC_PLL4FRACR_FRACV_6 (0x40U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000200 */ +#define RCC_PLL4FRACR_FRACV_7 (0x80U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000400 */ +#define RCC_PLL4FRACR_FRACV_8 (0x100U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00000800 */ +#define RCC_PLL4FRACR_FRACV_9 (0x200U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00001000 */ +#define RCC_PLL4FRACR_FRACV_10 (0x400U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00002000 */ +#define RCC_PLL4FRACR_FRACV_11 (0x800U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00004000 */ +#define RCC_PLL4FRACR_FRACV_12 (0x1000U << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x00008000 */ +#define RCC_PLL4FRACR_FRACLE_Pos (16U) +#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */ +#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*!< PLL4 fractional latch enable */ /******************** Bit definition for RCC_PLL4CSGR register********************/ #define RCC_PLL4CSGR_MOD_PER_Pos (0U) @@ -22043,1959 +28444,2853 @@ typedef struct #define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */ #define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/ -/******************** Bit definition for RCC_I2C12CKSELR register********************/ -#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) -#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/ -#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C35CKSELR register********************/ -#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) -#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/ -#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_I2C46CKSELR register********************/ -#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U) -#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */ -#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/ -#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */ -#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */ -#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */ -#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SAI1CKSELR register********************/ -#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) -#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/ -#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI2CKSELR register********************/ -#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) -#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/ -#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ -#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SAI3CKSELR register********************/ -#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) -#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/ -#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SAI4CKSELR register********************/ -#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) -#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ -#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/ -#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */ -#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ -#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ -#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */ -#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S1CKSELR register********************/ -#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) -#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/ -#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI2S23CKSELR register********************/ -#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) -#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/ -#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI45CKSELR register********************/ -#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) -#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/ -#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_SPI6CKSELR register********************/ -#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U) -#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */ -#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/ -#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */ -#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */ -#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */ -#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */ -#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */ -#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_UART6CKSELR register********************/ -#define RCC_UART6CKSELR_UART6SRC_Pos (0U) -#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/ -#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART24CKSELR register********************/ -#define RCC_UART24CKSELR_UART24SRC_Pos (0U) -#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/ -#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART35CKSELR register********************/ -#define RCC_UART35CKSELR_UART35SRC_Pos (0U) -#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/ -#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART78CKSELR register********************/ -#define RCC_UART78CKSELR_UART78SRC_Pos (0U) -#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/ -#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ - -/******************** Bit definition for RCC_UART1CKSELR register********************/ -#define RCC_UART1CKSELR_UART1SRC_Pos (0U) -#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */ -#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/ -#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */ -#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */ -#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */ -#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */ -#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */ -#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_SDMMC12CKSELR register********************/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) -#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SDMMC3CKSELR register********************/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) -#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ -#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_ETHCKSELR register********************/ -#define RCC_ETHCKSELR_ETHSRC_Pos (0U) -#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ -#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/ -#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ -#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ - -#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) -#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ -#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/ -#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */ -#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ -#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ -#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */ -#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ -#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */ -#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */ -#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */ -#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ -#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */ -#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */ -#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ - -/******************** Bit definition for RCC_QSPICKSELR register********************/ -#define RCC_QSPICKSELR_QSPISRC_Pos (0U) -#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ -#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/ -#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */ -#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ -#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ -#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FMCCKSELR register********************/ -#define RCC_FMCCKSELR_FMCSRC_Pos (0U) -#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ -#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/ -#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */ -#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ -#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ -#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_FDCANCKSELR register********************/ -#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) -#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ -#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/ -#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */ -#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ -#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ -#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_SPDIFCKSELR register********************/ -#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) -#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ -#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/ -#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ -#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_CECCKSELR register********************/ -#define RCC_CECCKSELR_CECSRC_Pos (0U) -#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ -#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/ -#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */ -#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ -#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_USBCKSELR register********************/ -#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) -#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ -#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/ -#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ -#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ - -#define RCC_USBCKSELR_USBOSRC_Pos (4U) -#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ -#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/ -#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */ -#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ - -/******************** Bit definition for RCC_RNG1CKSELR register********************/ -#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U) -#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/ -#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_RNG2CKSELR register********************/ -#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) -#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ -#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/ -#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */ -#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ -#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ -#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CPERCKSELR register********************/ -#define RCC_CPERCKSELR_CKPERSRC_Pos (0U) -#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ -#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */ -#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */ -#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */ -#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */ - -/******************** Bit definition for RCC_CSTGENCKSELR register******************/ -#define RCC_STGENCKSELR_STGENSRC_Pos (0U) -#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */ -#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/ -#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */ -#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */ -#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_DDRITFCR register*********************/ -#define RCC_DDRITFCR_DDRC1EN B(0) -#define RCC_DDRITFCR_DDRC1LPEN B(1) -#define RCC_DDRITFCR_DDRC2EN B(2) -#define RCC_DDRITFCR_DDRC2LPEN B(3) -#define RCC_DDRITFCR_DDRPHYCEN B(4) -#define RCC_DDRITFCR_DDRPHYCLPEN B(5) -#define RCC_DDRITFCR_DDRCAPBEN B(6) -#define RCC_DDRITFCR_DDRCAPBLPEN B(7) -#define RCC_DDRITFCR_AXIDCGEN B(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN B(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10) - -#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U) -#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ -#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/ -#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */ -#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */ -#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */ -#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */ -#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */ -#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */ -#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */ -#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */ -#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */ -#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */ -#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */ -#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */ -#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */ - -#define RCC_DDRITFCR_DDRCAPBRST B(14) -#define RCC_DDRITFCR_DDRCAXIRST B(15) -#define RCC_DDRITFCR_DDRCORERST B(16) -#define RCC_DDRITFCR_DPHYAPBRST B(17) -#define RCC_DDRITFCR_DPHYRST B(18) -#define RCC_DDRITFCR_DPHYCTLRST B(19) - -#define RCC_DDRITFCR_DDRCKMOD_Pos (20U) -#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */ -#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/ -#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */ -#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */ -#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */ -#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */ -#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */ - -/******************** Bit definition for RCC_DSICKSELR register********************/ -#define RCC_DSICKSELR_DSISRC_Pos (0U) -#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ -#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/ -#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */ -#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_ADCCKSELR register********************/ -#define RCC_ADCCKSELR_ADCSRC_Pos (0U) -#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ -#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/ -#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */ -#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ -#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ - -/******************** Bit definition for RCC_LPTIM45CKSELR register********************/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) -#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_LPTIM23CKSELR register********************/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) -#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */ - -/******************** Bit definition for RCC_LPTIM1CKSELR register********************/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) -#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */ -#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */ - -/******************** Bit definition for RCC_MP_BOOTCR register*********************/ -#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U) -#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/ -#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U) -#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */ -#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/ - -/******************** Bit definition for RCC_MP_SREQSETR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_SREQCLRR register********************/ -/* @note The MCU cannot access to this register */ -#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U) -#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */ -#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/ -#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U) -#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */ -#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/ - -/******************** Bit definition for RCC_MP_GCR register********************/ -#define RCC_MP_GCR_BOOT_MCU_Pos (0U) -#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ -#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/ -#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */ -#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */ - -/******************** Bit definition for RCC_MP_APRSTCR register ********************/ -#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U) -#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */ -#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/ -#define RCC_MP_APRSTCR_RSTTO_Pos (8U) -#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/ - -/******************** Bit definition for RCC_MP_APRSTSR register ********************/ -#define RCC_MP_APRSTSR_RSTTOV_Pos (8U) -#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */ -#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/ - -/******************* Bit definition for RCC_BDCR register ********************/ -#define RCC_BDCR_LSEON_Pos (0U) -#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ -#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/ -#define RCC_BDCR_LSEBYP_Pos (1U) -#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */ -#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/ -#define RCC_BDCR_LSERDY_Pos (2U) -#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */ -#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/ - -#define RCC_BDCR_DIGBYP_Pos (3U) -#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */ -#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */ - -#define RCC_BDCR_LSEDRV_Pos (4U) -#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ -#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/ -#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ -#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */ -#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */ - -#define RCC_BDCR_LSECSSON_Pos (8U) -#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */ -#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/ -#define RCC_BDCR_LSECSSD_Pos (9U) -#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */ -#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/ - -#define RCC_BDCR_RTCSRC_Pos (16U) -#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ -#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/ -#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */ -#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */ -#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */ -#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */ - -#define RCC_BDCR_RTCCKEN_Pos (20U) -#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */ -#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/ -#define RCC_BDCR_VSWRST_Pos (31U) -#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */ -#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/ - -/******************* Bit definition for RCC_RDLSICR register ********************/ -#define RCC_RDLSICR_LSION_Pos (0U) -#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */ -#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/ -#define RCC_RDLSICR_LSIRDY_Pos (1U) -#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */ -#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/ -#define RCC_RDLSICR_MRD_Pos (16U) -#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */ -#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/ -#define RCC_RDLSICR_EADLY_Pos (24U) -#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */ -#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/ -#define RCC_RDLSICR_SPARE_Pos (27U) -#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */ -#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_CIER register *******************/ -#define RCC_MP_CIER_LSIRDYIE_Pos (0U) -#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MP_CIER_LSERDYIE_Pos (1U) -#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MP_CIER_HSIRDYIE_Pos (2U) -#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MP_CIER_HSERDYIE_Pos (3U) -#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MP_CIER_CSIRDYIE_Pos (4U) -#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL1DYIE_Pos (8U) -#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL2DYIE_Pos (9U) -#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL3DYIE_Pos (10U) -#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_PLL4DYIE_Pos (11U) -#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MP_CIER_LSECSSIE_Pos (16U) -#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MP_CIER_WKUPIE_Pos (20U) -#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MP_CIFR register ********************/ -#define RCC_MP_CIFR_LSIRDYF_Pos (0U) -#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSERDYF_Pos (1U) -#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSIRDYF_Pos (2U) -#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_HSERDYF_Pos (3U) -#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MP_CIFR_CSIRDYF_Pos (4U) -#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL1DYF_Pos (8U) -#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL2DYF_Pos (9U) -#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL3DYF_Pos (10U) -#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MP_CIFR_PLL4DYF_Pos (11U) -#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MP_CIFR_LSECSSF_Pos (16U) -#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MP_CIFR_WKUPF_Pos (20U) -#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - -/******************* Bit definition for RCC_MC_CIER register *******************/ -#define RCC_MC_CIER_LSIRDYIE_Pos (0U) -#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/ -#define RCC_MC_CIER_LSERDYIE_Pos (1U) -#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/ -#define RCC_MC_CIER_HSIRDYIE_Pos (2U) -#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/ -#define RCC_MC_CIER_HSERDYIE_Pos (3U) -#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/ -#define RCC_MC_CIER_CSIRDYIE_Pos (4U) -#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL1DYIE_Pos (8U) -#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL2DYIE_Pos (9U) -#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL3DYIE_Pos (10U) -#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_PLL4DYIE_Pos (11U) -#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/ -#define RCC_MC_CIER_LSECSSIE_Pos (16U) -#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/ -#define RCC_MC_CIER_WKUPIE_Pos (20U) -#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/ - -/******************* Bit definition for RCC_MC_CIFR register ********************/ -#define RCC_MC_CIFR_LSIRDYF_Pos (0U) -#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ -#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSERDYF_Pos (1U) -#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ -#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSIRDYF_Pos (2U) -#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ -#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_HSERDYF_Pos (3U) -#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ -#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/ -#define RCC_MC_CIFR_CSIRDYF_Pos (4U) -#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ -#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL1DYF_Pos (8U) -#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ -#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL2DYF_Pos (9U) -#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ -#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL3DYF_Pos (10U) -#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ -#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/ -#define RCC_MC_CIFR_PLL4DYF_Pos (11U) -#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ -#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/ -#define RCC_MC_CIFR_LSECSSF_Pos (16U) -#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ -#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/ -#define RCC_MC_CIFR_WKUPF_Pos (20U) -#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ -#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/ - - -/******************* Bit definition for RCC_PWRLPDLYCR register ********************/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/ -#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U) -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */ -#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/ - -#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/ - - -/******************* Bit definition for RCC_MP_RSTSSETR register *********************/ -/*!< This register is dedicated to the BOOTROM code in order to update the reset source. - * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a - * system reset (nreset), or an exit from Standby or CStandby. - *@note The application software shall not use this register. In order to identify the - * reset source, the MPU application must use RCC MPU Reset Status Clear Register - * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status - * Clear Register (RCC_MC_RSTSCLRR). - *@note Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '1'. - *@note The register is located in VDDCORE. - *@note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSSETR_SPARE_Pos (15U) -#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_APB1RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB1RSTSETR_TIM2RST B(0) -#define RCC_APB1RSTSETR_TIM3RST B(1) -#define RCC_APB1RSTSETR_TIM4RST B(2) -#define RCC_APB1RSTSETR_TIM5RST B(3) -#define RCC_APB1RSTSETR_TIM6RST B(4) -#define RCC_APB1RSTSETR_TIM7RST B(5) -#define RCC_APB1RSTSETR_TIM12RST B(6) -#define RCC_APB1RSTSETR_TIM13RST B(7) -#define RCC_APB1RSTSETR_TIM14RST B(8) -#define RCC_APB1RSTSETR_LPTIM1RST B(9) -#define RCC_APB1RSTSETR_SPI2RST B(11) -#define RCC_APB1RSTSETR_SPI3RST B(12) -#define RCC_APB1RSTSETR_USART2RST B(14) -#define RCC_APB1RSTSETR_USART3RST B(15) -#define RCC_APB1RSTSETR_UART4RST B(16) -#define RCC_APB1RSTSETR_UART5RST B(17) -#define RCC_APB1RSTSETR_UART7RST B(18) -#define RCC_APB1RSTSETR_UART8RST B(19) -#define RCC_APB1RSTSETR_I2C1RST B(21) -#define RCC_APB1RSTSETR_I2C2RST B(22) -#define RCC_APB1RSTSETR_I2C3RST B(23) -#define RCC_APB1RSTSETR_I2C5RST B(24) -#define RCC_APB1RSTSETR_SPDIFRST B(26) -#define RCC_APB1RSTSETR_CECRST B(27) -#define RCC_APB1RSTSETR_DAC12RST B(29) -#define RCC_APB1RSTSETR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB1RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB1RSTCLRR_TIM2RST B(0) -#define RCC_APB1RSTCLRR_TIM3RST B(1) -#define RCC_APB1RSTCLRR_TIM4RST B(2) -#define RCC_APB1RSTCLRR_TIM5RST B(3) -#define RCC_APB1RSTCLRR_TIM6RST B(4) -#define RCC_APB1RSTCLRR_TIM7RST B(5) -#define RCC_APB1RSTCLRR_TIM12RST B(6) -#define RCC_APB1RSTCLRR_TIM13RST B(7) -#define RCC_APB1RSTCLRR_TIM14RST B(8) -#define RCC_APB1RSTCLRR_LPTIM1RST B(9) -#define RCC_APB1RSTCLRR_SPI2RST B(11) -#define RCC_APB1RSTCLRR_SPI3RST B(12) -#define RCC_APB1RSTCLRR_USART2RST B(14) -#define RCC_APB1RSTCLRR_USART3RST B(15) -#define RCC_APB1RSTCLRR_UART4RST B(16) -#define RCC_APB1RSTCLRR_UART5RST B(17) -#define RCC_APB1RSTCLRR_UART7RST B(18) -#define RCC_APB1RSTCLRR_UART8RST B(19) -#define RCC_APB1RSTCLRR_I2C1RST B(21) -#define RCC_APB1RSTCLRR_I2C2RST B(22) -#define RCC_APB1RSTCLRR_I2C3RST B(23) -#define RCC_APB1RSTCLRR_I2C5RST B(24) -#define RCC_APB1RSTCLRR_SPDIFRST B(26) -#define RCC_APB1RSTCLRR_CECRST B(27) -#define RCC_APB1RSTCLRR_DAC12RST B(29) -#define RCC_APB1RSTCLRR_MDIOSRST B(31) - -/******************* Bit definition for RCC_APB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB2RSTSETR_TIM1RST B(0) -#define RCC_APB2RSTSETR_TIM8RST B(1) -#define RCC_APB2RSTSETR_TIM15RST B(2) -#define RCC_APB2RSTSETR_TIM16RST B(3) -#define RCC_APB2RSTSETR_TIM17RST B(4) -#define RCC_APB2RSTSETR_SPI1RST B(8) -#define RCC_APB2RSTSETR_SPI4RST B(9) -#define RCC_APB2RSTSETR_SPI5RST B(10) -#define RCC_APB2RSTSETR_USART6RST B(13) -#define RCC_APB2RSTSETR_SAI1RST B(16) -#define RCC_APB2RSTSETR_SAI2RST B(17) -#define RCC_APB2RSTSETR_SAI3RST B(18) -#define RCC_APB2RSTSETR_DFSDMRST B(20) -#define RCC_APB2RSTSETR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB2RSTCLRR_TIM1RST B(0) -#define RCC_APB2RSTCLRR_TIM8RST B(1) -#define RCC_APB2RSTCLRR_TIM15RST B(2) -#define RCC_APB2RSTCLRR_TIM16RST B(3) -#define RCC_APB2RSTCLRR_TIM17RST B(4) -#define RCC_APB2RSTCLRR_SPI1RST B(8) -#define RCC_APB2RSTCLRR_SPI4RST B(9) -#define RCC_APB2RSTCLRR_SPI5RST B(10) -#define RCC_APB2RSTCLRR_USART6RST B(13) -#define RCC_APB2RSTCLRR_SAI1RST B(16) -#define RCC_APB2RSTCLRR_SAI2RST B(17) -#define RCC_APB2RSTCLRR_SAI3RST B(18) -#define RCC_APB2RSTCLRR_DFSDMRST B(20) -#define RCC_APB2RSTCLRR_FDCANRST B(24) - -/******************* Bit definition for RCC_APB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB3RSTSETR_LPTIM2RST B(0) -#define RCC_APB3RSTSETR_LPTIM3RST B(1) -#define RCC_APB3RSTSETR_LPTIM4RST B(2) -#define RCC_APB3RSTSETR_LPTIM5RST B(3) -#define RCC_APB3RSTSETR_SAI4RST B(8) -#define RCC_APB3RSTSETR_SYSCFGRST B(11) -#define RCC_APB3RSTSETR_VREFRST B(13) -#define RCC_APB3RSTSETR_DTSRST B(16) -#define RCC_APB3RSTSETR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_APB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB3RSTCLRR_LPTIM2RST B(0) -#define RCC_APB3RSTCLRR_LPTIM3RST B(1) -#define RCC_APB3RSTCLRR_LPTIM4RST B(2) -#define RCC_APB3RSTCLRR_LPTIM5RST B(3) -#define RCC_APB3RSTCLRR_SAI4RST B(8) -#define RCC_APB3RSTCLRR_SYSCFGRST B(11) -#define RCC_APB3RSTCLRR_VREFRST B(13) -#define RCC_APB3RSTCLRR_DTSRST B(16) -#define RCC_APB3RSTCLRR_PMBCTRLRST B(17) - -/******************* Bit definition for RCC_AHB2RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB2RSTSETR_DMA1RST B(0) -#define RCC_AHB2RSTSETR_DMA2RST B(1) -#define RCC_AHB2RSTSETR_DMAMUXRST B(2) -#define RCC_AHB2RSTSETR_ADC12RST B(5) -#define RCC_AHB2RSTSETR_USBORST B(8) -#define RCC_AHB2RSTSETR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB2RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB2RSTCLRR_DMA1RST B(0) -#define RCC_AHB2RSTCLRR_DMA2RST B(1) -#define RCC_AHB2RSTCLRR_DMAMUXRST B(2) -#define RCC_AHB2RSTCLRR_ADC12RST B(5) -#define RCC_AHB2RSTCLRR_USBORST B(8) -#define RCC_AHB2RSTCLRR_SDMMC3RST B(16) - -/******************* Bit definition for RCC_AHB3RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB3RSTSETR_DCMIRST B(0) -#define RCC_AHB3RSTSETR_CRYP2RST B(4) -#define RCC_AHB3RSTSETR_HASH2RST B(5) -#define RCC_AHB3RSTSETR_RNG2RST B(6) -#define RCC_AHB3RSTSETR_CRC2RST B(7) -#define RCC_AHB3RSTSETR_HSEMRST B(11) -#define RCC_AHB3RSTSETR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB3RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB3RSTCLRR_DCMIRST B(0) -#define RCC_AHB3RSTCLRR_CRYP2RST B(4) -#define RCC_AHB3RSTCLRR_HASH2RST B(5) -#define RCC_AHB3RSTCLRR_RNG2RST B(6) -#define RCC_AHB3RSTCLRR_CRC2RST B(7) -#define RCC_AHB3RSTCLRR_HSEMRST B(11) -#define RCC_AHB3RSTCLRR_IPCCRST B(12) - -/******************* Bit definition for RCC_AHB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB4RSTSETR_GPIOARST B(0) -#define RCC_AHB4RSTSETR_GPIOBRST B(1) -#define RCC_AHB4RSTSETR_GPIOCRST B(2) -#define RCC_AHB4RSTSETR_GPIODRST B(3) -#define RCC_AHB4RSTSETR_GPIOERST B(4) -#define RCC_AHB4RSTSETR_GPIOFRST B(5) -#define RCC_AHB4RSTSETR_GPIOGRST B(6) -#define RCC_AHB4RSTSETR_GPIOHRST B(7) -#define RCC_AHB4RSTSETR_GPIOIRST B(8) -#define RCC_AHB4RSTSETR_GPIOJRST B(9) -#define RCC_AHB4RSTSETR_GPIOKRST B(10) - -/******************* Bit definition for RCC_AHB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB4RSTCLRR_GPIOARST B(0) -#define RCC_AHB4RSTCLRR_GPIOBRST B(1) -#define RCC_AHB4RSTCLRR_GPIOCRST B(2) -#define RCC_AHB4RSTCLRR_GPIODRST B(3) -#define RCC_AHB4RSTCLRR_GPIOERST B(4) -#define RCC_AHB4RSTCLRR_GPIOFRST B(5) -#define RCC_AHB4RSTCLRR_GPIOGRST B(6) -#define RCC_AHB4RSTCLRR_GPIOHRST B(7) -#define RCC_AHB4RSTCLRR_GPIOIRST B(8) -#define RCC_AHB4RSTCLRR_GPIOJRST B(9) -#define RCC_AHB4RSTCLRR_GPIOKRST B(10) - -/******************* Bit definition for RCC_APB4RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB4RSTSETR_LTDCRST B(0) -#define RCC_APB4RSTSETR_DSIRST B(4) -#define RCC_APB4RSTSETR_DDRPERFMRST B(8) -#define RCC_APB4RSTSETR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB4RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB4RSTCLRR_LTDCRST B(0) -#define RCC_APB4RSTCLRR_DSIRST B(4) -#define RCC_APB4RSTCLRR_DDRPERFMRST B(8) -#define RCC_APB4RSTCLRR_USBPHYRST B(16) - -/******************* Bit definition for RCC_APB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_APB5RSTSETR_SPI6RST B(0) -#define RCC_APB5RSTSETR_I2C4RST B(2) -#define RCC_APB5RSTSETR_I2C6RST B(3) -#define RCC_APB5RSTSETR_USART1RST B(4) -#define RCC_APB5RSTSETR_STGENRST B(20) - -/******************* Bit definition for RCC_APB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_APB5RSTCLRR_SPI6RST B(0) -#define RCC_APB5RSTCLRR_I2C4RST B(2) -#define RCC_APB5RSTCLRR_I2C6RST B(3) -#define RCC_APB5RSTCLRR_USART1RST B(4) -#define RCC_APB5RSTCLRR_STGENRST B(20) - -/******************* Bit definition for RCC_AHB5RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB5RSTSETR_GPIOZRST B(0) -#define RCC_AHB5RSTSETR_CRYP1RST B(4) -#define RCC_AHB5RSTSETR_HASH1RST B(5) -#define RCC_AHB5RSTSETR_RNG1RST B(6) -#define RCC_AHB5RSTSETR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB5RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB5RSTCLRR_GPIOZRST B(0) -#define RCC_AHB5RSTCLRR_CRYP1RST B(4) -#define RCC_AHB5RSTCLRR_HASH1RST B(5) -#define RCC_AHB5RSTCLRR_RNG1RST B(6) -#define RCC_AHB5RSTCLRR_AXIMCRST B(16) - -/******************* Bit definition for RCC_AHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_AHB6RSTSETR_GPURST B(5) -#define RCC_AHB6RSTSETR_ETHMACRST B(10) -#define RCC_AHB6RSTSETR_FMCRST B(12) -#define RCC_AHB6RSTSETR_QSPIRST B(14) -#define RCC_AHB6RSTSETR_SDMMC1RST B(16) -#define RCC_AHB6RSTSETR_SDMMC2RST B(17) -#define RCC_AHB6RSTSETR_CRC1RST B(20) -#define RCC_AHB6RSTSETR_USBHRST B(24) - -/******************* Bit definition for RCC_AHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_AHB6RSTCLRR_ETHMACRST B(10) -#define RCC_AHB6RSTCLRR_FMCRST B(12) -#define RCC_AHB6RSTCLRR_QSPIRST B(14) -#define RCC_AHB6RSTCLRR_SDMMC1RST B(16) -#define RCC_AHB6RSTCLRR_SDMMC2RST B(17) -#define RCC_AHB6RSTCLRR_CRC1RST B(20) -#define RCC_AHB6RSTCLRR_USBHRST B(24) - -/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/ -/*!< This register is used to activate the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTSETR_MDMARST B(0) - -/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/ -/*!< This register is used to release the reset of the corresponding peripheral */ -#define RCC_TZAHB6RSTCLRR_MDMARST B(0) - -/******************* Bit definition for RCC_MP_GRSTCSETR register ************/ -/*!< This register is used by the MPU in order to generate either a MCU reset - * or a system reset or a reset of one of the two MPU processors. Writing '0' has - * no effect, reading will return the effective values of the corresponding bits. - * Writing a '1' activates the reset */ -#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U) -#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */ -#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */ -#define RCC_MP_GRSTCSETR_MCURST_Pos (1U) -#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */ -#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */ -#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U) -#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */ -#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/ -#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U) -#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */ -#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/ - -/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB1ENSETR_TIM2EN B(0) -#define RCC_MC_APB1ENSETR_TIM3EN B(1) -#define RCC_MC_APB1ENSETR_TIM4EN B(2) -#define RCC_MC_APB1ENSETR_TIM5EN B(3) -#define RCC_MC_APB1ENSETR_TIM6EN B(4) -#define RCC_MC_APB1ENSETR_TIM7EN B(5) -#define RCC_MC_APB1ENSETR_TIM12EN B(6) -#define RCC_MC_APB1ENSETR_TIM13EN B(7) -#define RCC_MC_APB1ENSETR_TIM14EN B(8) -#define RCC_MC_APB1ENSETR_LPTIM1EN B(9) -#define RCC_MC_APB1ENSETR_SPI2EN B(11) -#define RCC_MC_APB1ENSETR_SPI3EN B(12) -#define RCC_MC_APB1ENSETR_USART2EN B(14) -#define RCC_MC_APB1ENSETR_USART3EN B(15) -#define RCC_MC_APB1ENSETR_UART4EN B(16) -#define RCC_MC_APB1ENSETR_UART5EN B(17) -#define RCC_MC_APB1ENSETR_UART7EN B(18) -#define RCC_MC_APB1ENSETR_UART8EN B(19) -#define RCC_MC_APB1ENSETR_I2C1EN B(21) -#define RCC_MC_APB1ENSETR_I2C2EN B(22) -#define RCC_MC_APB1ENSETR_I2C3EN B(23) -#define RCC_MC_APB1ENSETR_I2C5EN B(24) -#define RCC_MC_APB1ENSETR_SPDIFEN B(26) -#define RCC_MC_APB1ENSETR_CECEN B(27) -#define RCC_MC_APB1ENSETR_WWDG1EN B(28) -#define RCC_MC_APB1ENSETR_DAC12EN B(29) -#define RCC_MC_APB1ENSETR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding -peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB1ENCLRR_TIM2EN B(0) -#define RCC_MC_APB1ENCLRR_TIM3EN B(1) -#define RCC_MC_APB1ENCLRR_TIM4EN B(2) -#define RCC_MC_APB1ENCLRR_TIM5EN B(3) -#define RCC_MC_APB1ENCLRR_TIM6EN B(4) -#define RCC_MC_APB1ENCLRR_TIM7EN B(5) -#define RCC_MC_APB1ENCLRR_TIM12EN B(6) -#define RCC_MC_APB1ENCLRR_TIM13EN B(7) -#define RCC_MC_APB1ENCLRR_TIM14EN B(8) -#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9) -#define RCC_MC_APB1ENCLRR_SPI2EN B(11) -#define RCC_MC_APB1ENCLRR_SPI3EN B(12) -#define RCC_MC_APB1ENCLRR_USART2EN B(14) -#define RCC_MC_APB1ENCLRR_USART3EN B(15) -#define RCC_MC_APB1ENCLRR_UART4EN B(16) -#define RCC_MC_APB1ENCLRR_UART5EN B(17) -#define RCC_MC_APB1ENCLRR_UART7EN B(18) -#define RCC_MC_APB1ENCLRR_UART8EN B(19) -#define RCC_MC_APB1ENCLRR_I2C1EN B(21) -#define RCC_MC_APB1ENCLRR_I2C2EN B(22) -#define RCC_MC_APB1ENCLRR_I2C3EN B(23) -#define RCC_MC_APB1ENCLRR_I2C5EN B(24) -#define RCC_MC_APB1ENCLRR_SPDIFEN B(26) -#define RCC_MC_APB1ENCLRR_CECEN B(27) -#define RCC_MC_APB1ENCLRR_WWDG1EN B(28) -#define RCC_MC_APB1ENCLRR_DAC12EN B(29) -#define RCC_MC_APB1ENCLRR_MDIOSEN B(31) - -/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB2ENSETR_TIM1EN B(0) -#define RCC_MC_APB2ENSETR_TIM8EN B(1) -#define RCC_MC_APB2ENSETR_TIM15EN B(2) -#define RCC_MC_APB2ENSETR_TIM16EN B(3) -#define RCC_MC_APB2ENSETR_TIM17EN B(4) -#define RCC_MC_APB2ENSETR_SPI1EN B(8) -#define RCC_MC_APB2ENSETR_SPI4EN B(9) -#define RCC_MC_APB2ENSETR_SPI5EN B(10) -#define RCC_MC_APB2ENSETR_USART6EN B(13) -#define RCC_MC_APB2ENSETR_SAI1EN B(16) -#define RCC_MC_APB2ENSETR_SAI2EN B(17) -#define RCC_MC_APB2ENSETR_SAI3EN B(18) -#define RCC_MC_APB2ENSETR_DFSDMEN B(20) -#define RCC_MC_APB2ENSETR_ADFSDMEN B(21) -#define RCC_MC_APB2ENSETR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB2ENCLRR_TIM1EN B(0) -#define RCC_MC_APB2ENCLRR_TIM8EN B(1) -#define RCC_MC_APB2ENCLRR_TIM15EN B(2) -#define RCC_MC_APB2ENCLRR_TIM16EN B(3) -#define RCC_MC_APB2ENCLRR_TIM17EN B(4) -#define RCC_MC_APB2ENCLRR_SPI1EN B(8) -#define RCC_MC_APB2ENCLRR_SPI4EN B(9) -#define RCC_MC_APB2ENCLRR_SPI5EN B(10) -#define RCC_MC_APB2ENCLRR_USART6EN B(13) -#define RCC_MC_APB2ENCLRR_SAI1EN B(16) -#define RCC_MC_APB2ENCLRR_SAI2EN B(17) -#define RCC_MC_APB2ENCLRR_SAI3EN B(18) -#define RCC_MC_APB2ENCLRR_DFSDMEN B(20) -#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21) -#define RCC_MC_APB2ENCLRR_FDCANEN B(24) - -/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB3ENSETR_LPTIM2EN B(0) -#define RCC_MC_APB3ENSETR_LPTIM3EN B(1) -#define RCC_MC_APB3ENSETR_LPTIM4EN B(2) -#define RCC_MC_APB3ENSETR_LPTIM5EN B(3) -#define RCC_MC_APB3ENSETR_SAI4EN B(8) -#define RCC_MC_APB3ENSETR_SYSCFGEN B(11) -#define RCC_MC_APB3ENSETR_VREFEN B(13) -#define RCC_MC_APB3ENSETR_DTSEN B(16) -#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENSETR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0) -#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1) -#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2) -#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3) -#define RCC_MC_APB3ENCLRR_SAI4EN B(8) -#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11) -#define RCC_MC_APB3ENCLRR_VREFEN B(13) -#define RCC_MC_APB3ENCLRR_DTSEN B(16) -#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17) -#define RCC_MC_APB3ENCLRR_HDPEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB4ENSETR_LTDCEN B(0) -#define RCC_MC_APB4ENSETR_DSIEN B(4) -#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8) -#define RCC_MC_APB4ENSETR_USBPHYEN B(16) -#define RCC_MC_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_APB4ENSETR_LTDCEN B(0) -#define RCC_MP_APB4ENSETR_DSIEN B(4) -#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENSETR_USBPHYEN B(16) -#define RCC_MP_APB4ENSETR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB4ENCLRR_LTDCEN B(0) -#define RCC_MC_APB4ENCLRR_DSIEN B(4) -#define RCC_MC_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MC_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MP_APB4ENCLRR_LTDCEN B(0) -#define RCC_MP_APB4ENCLRR_DSIEN B(4) -#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15) -#define RCC_MP_APB4ENCLRR_USBPHYEN B(16) -#define RCC_MP_APB4ENCLRR_STGENROEN B(20) - -/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_APB5ENSETR_SPI6EN B(0) -#define RCC_MC_APB5ENSETR_I2C4EN B(2) -#define RCC_MC_APB5ENSETR_I2C6EN B(3) -#define RCC_MC_APB5ENSETR_USART1EN B(4) -#define RCC_MC_APB5ENSETR_RTCAPBEN B(8) -#define RCC_MC_APB5ENSETR_TZC1EN B(11) -#define RCC_MC_APB5ENSETR_TZC2EN B(12) -#define RCC_MC_APB5ENSETR_TZPCEN B(13) -#define RCC_MC_APB5ENSETR_BSECEN B(16) -#define RCC_MC_APB5ENSETR_STGENEN B(20) - -/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. - * This bit can also be used to test if IWDG1 peripheral clock is enabled - * If TZEN = 1, this register can only be modified in secure mode. */ -#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15) - -/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_APB5ENCLRR_SPI6EN B(0) -#define RCC_MC_APB5ENCLRR_I2C4EN B(2) -#define RCC_MC_APB5ENCLRR_I2C6EN B(3) -#define RCC_MC_APB5ENCLRR_USART1EN B(4) -#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8) -#define RCC_MC_APB5ENCLRR_TZC1EN B(11) -#define RCC_MC_APB5ENCLRR_TZC2EN B(12) -#define RCC_MC_APB5ENCLRR_TZPCEN B(13) -#define RCC_MC_APB5ENCLRR_BSECEN B(16) -#define RCC_MC_APB5ENCLRR_STGENEN B(20) - -/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB5ENSETR_GPIOZEN B(0) -#define RCC_MC_AHB5ENSETR_CRYP1EN B(4) -#define RCC_MC_AHB5ENSETR_HASH1EN B(5) -#define RCC_MC_AHB5ENSETR_RNG1EN B(6) -#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8) -#define RCC_MC_AHB5ENSETR_AXIMC B(16) - -/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0) -#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4) -#define RCC_MC_AHB5ENCLRR_HASH1EN B(5) -#define RCC_MC_AHB5ENCLRR_RNG1EN B(6) -#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8) - -/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB6ENSETR_MDMAEN B(0) -#define RCC_MC_AHB6ENSETR_GPUEN B(5) -#define RCC_MC_AHB6ENSETR_ETHCKEN B(7) -#define RCC_MC_AHB6ENSETR_ETHTXEN B(8) -#define RCC_MC_AHB6ENSETR_ETHRXEN B(9) -#define RCC_MC_AHB6ENSETR_ETHMACEN B(10) -#define RCC_MC_AHB6ENSETR_FMCEN B(12) -#define RCC_MC_AHB6ENSETR_QSPIEN B(14) -#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENSETR_CRC1EN B(20) -#define RCC_MC_AHB6ENSETR_USBHEN B(24) - -/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB6ENCLRR_MDMAEN B(0) -#define RCC_MC_AHB6ENCLRR_GPUEN B(5) -#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7) -#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8) -#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9) -#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10) -#define RCC_MC_AHB6ENCLRR_FMCEN B(12) -#define RCC_MC_AHB6ENCLRR_QSPIEN B(14) -#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16) -#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17) -#define RCC_MC_AHB6ENCLRR_CRC1EN B(20) -#define RCC_MC_AHB6ENCLRR_USBHEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */ -#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MPU */ -#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0) - -/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB2ENSETR_DMA1EN B(0) -#define RCC_MC_AHB2ENSETR_DMA2EN B(1) -#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENSETR_ADC12EN B(5) -#define RCC_MC_AHB2ENSETR_USBOEN B(8) -#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB2ENCLRR_DMA1EN B(0) -#define RCC_MC_AHB2ENCLRR_DMA2EN B(1) -#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2) -#define RCC_MC_AHB2ENCLRR_ADC12EN B(5) -#define RCC_MC_AHB2ENCLRR_USBOEN B(8) -#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16) - -/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB3ENSETR_DCMIEN B(0) -#define RCC_MC_AHB3ENSETR_CRYP2EN B(4) -#define RCC_MC_AHB3ENSETR_HASH2EN B(5) -#define RCC_MC_AHB3ENSETR_RNG2EN B(6) -#define RCC_MC_AHB3ENSETR_CRC2EN B(7) -#define RCC_MC_AHB3ENSETR_HSEMEN B(11) -#define RCC_MC_AHB3ENSETR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB3ENCLRR_DCMIEN B(0) -#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4) -#define RCC_MC_AHB3ENCLRR_HASH2EN B(5) -#define RCC_MC_AHB3ENCLRR_RNG2EN B(6) -#define RCC_MC_AHB3ENCLRR_CRC2EN B(7) -#define RCC_MC_AHB3ENCLRR_HSEMEN B(11) -#define RCC_MC_AHB3ENCLRR_IPCCEN B(12) - -/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AHB4ENSETR_GPIOAEN B(0) -#define RCC_MC_AHB4ENSETR_GPIOBEN B(1) -#define RCC_MC_AHB4ENSETR_GPIOCEN B(2) -#define RCC_MC_AHB4ENSETR_GPIODEN B(3) -#define RCC_MC_AHB4ENSETR_GPIOEEN B(4) -#define RCC_MC_AHB4ENSETR_GPIOFEN B(5) -#define RCC_MC_AHB4ENSETR_GPIOGEN B(6) -#define RCC_MC_AHB4ENSETR_GPIOHEN B(7) -#define RCC_MC_AHB4ENSETR_GPIOIEN B(8) -#define RCC_MC_AHB4ENSETR_GPIOJEN B(9) -#define RCC_MC_AHB4ENSETR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0) -#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1) -#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2) -#define RCC_MC_AHB4ENCLRR_GPIODEN B(3) -#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4) -#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5) -#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6) -#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7) -#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8) -#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9) -#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10) - -/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_AXIMENSETR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/ -/*!< This register is used to set the peripheral clock enable bit of the corresponding - * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */ -#define RCC_MC_MLAHBENSETR_RETRAMEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/ -/*!< This register is used to clear the peripheral clock enable bit of the corresponding - * peripheral. It shall be used to deallocate a peripheral from MCU */ -#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4) - - -/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENSETR_USART2LPEN B(14) -#define RCC_MC_APB1LPENSETR_USART3LPEN B(15) -#define RCC_MC_APB1LPENSETR_UART4LPEN B(16) -#define RCC_MC_APB1LPENSETR_UART5LPEN B(17) -#define RCC_MC_APB1LPENSETR_UART7LPEN B(18) -#define RCC_MC_APB1LPENSETR_UART8LPEN B(19) -#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENSETR_CECLPEN B(27) -#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0) -#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1) -#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2) -#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3) -#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4) -#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5) -#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6) -#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7) -#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8) -#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9) -#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11) -#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12) -#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14) -#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15) -#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16) -#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17) -#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18) -#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19) -#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21) -#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22) -#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23) -#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24) -#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26) -#define RCC_MC_APB1LPENCLRR_CECLPEN B(27) -#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28) -#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29) -#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31) - -/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENSETR_USART6LPEN B(13) -#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0) -#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1) -#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2) -#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3) -#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4) -#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8) -#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9) -#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10) -#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13) -#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16) -#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17) -#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18) -#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20) -#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21) -#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24) - -/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENSETR_VREFLPEN B(13) -#define RCC_MC_APB3LPENSETR_DTSLPEN B(16) -#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0) -#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1) -#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2) -#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3) -#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8) -#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11) -#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13) -#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16) -#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17) - -/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENSETR_DSILPEN B(4) -#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/ -/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENSETR_DSILPEN B(4) -#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MC_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0) -#define RCC_MP_APB4LPENCLRR_DSILPEN B(4) -#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15) -#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16) -#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20) -#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21) - -/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENSETR_USART1LPEN B(4) -#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENSETR_BSECLPEN B(16) -#define RCC_MC_APB5LPENSETR_STGENLPEN B(20) -#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21) - - -/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0) -#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2) -#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3) -#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4) -#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8) -#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11) -#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12) -#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13) -#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16) -#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20) -#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21) - -/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0) -#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4) -#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5) -#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6) -#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8) - -/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENSETR_GPULPEN B(5) -#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0) -#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5) -#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7) -#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8) -#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9) -#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10) -#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11) -#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12) -#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14) -#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16) -#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17) -#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20) -#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24) - -/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0) - -/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0) -#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1) -#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2) -#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5) -#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8) -#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16) - -/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0) -#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4) -#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5) -#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6) -#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7) -#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11) -#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12) - -/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0) -#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1) -#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2) -#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3) -#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4) -#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5) -#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6) -#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7) -#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8) -#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9) -#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10) - -/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0) - -/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/ -/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding - * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in - * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */ -#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4) - -/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/ -/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding - * peripheral. Writing '0' has no effect, reading will return the effective values of the - * corresponding bits. Writing a '1' sets the corresponding bit to '0' */ -#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0) -#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1) -#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2) -#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4) - - -/******************* Bit definition for RCC_BR_RSTSCLRR register ************/ -/*!< This register is used by the BOOTROM to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a '1' clears the corresponding bit to '0' - * - * @note In order to identify the reset source, the MPU application must use - * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application - * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). - * @note This register except MPUP[1:0]RSTF flags is located into VDD domain, - * and is reset by por_rst reset. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - - -/******************* Bit definition for RCC_MC_RSTSCLRR register ************/ -/*!< This register is used by the MCU to check the reset source. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0 - * @note This register is located into VDD domain, and is reset by rst_por reset. - */ -#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) -#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/ - -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) -#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/ - -/******************* Bit definition for RCC_MP_RSTSCLRR register ************/ -/*!< This register is used by the MPU to check the reset source. This register is updated - * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or - * exit from STANDBY or CSTANDBY. - * - * @note Writing '0' has no effect, reading will return the effective values of - * the corresponding bits. Writing a '1' clears the corresponding bit to '0'. - * @note The register is located in VDD_CORE. - * @note If TZEN = '1', this register can only be modified in secure mode. - */ -#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U) -#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ -#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/ - -#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U) -#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ -#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/ - -#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U) -#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ -#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/ - -#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U) -#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ -#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/ - -#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U) -#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ -#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/ - -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U) -#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ -#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/ - -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U) -#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ -#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U) -#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ -#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/ - -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U) -#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ -#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/ - -#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U) -#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */ -#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/ - -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U) -#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */ -#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U) -#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */ -#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/ - -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U) -#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */ -#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/ - -#define RCC_MP_RSTSCLRR_SPARE_Pos (15U) -#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */ -#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/ - -/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/ -/*!< This register is used by the MPU in order to freeze the IWDGs clocks. - * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby) - * the MPU is allowed to write it once. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be - * modified in secure mode. - */ -#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1) - - -/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/ -/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks. - * Writing "0" has no effect, reading will return the effective values of the corresponding - * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only - * be modified in secure mode. - */ -#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0) -#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1) - -/******************* Bit definition for RCC_VERR register ************/ -/*!< This register gives the IP version. */ -#define RCC_VERR_MINREV_Pos (0U) -#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk -#define RCC_VERR_MAJREV_Pos (4U) -#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the unique identifier of the RCC */ -#define RCC_VERR_ID_Pos (0U) -#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_ID RCC_VERR_ID_Msk - -/******************* Bit definition for RCC_IDR register ************/ -/*!< This register gives the decoding space, which is for the RCC of 4 kB */ -#define RCC_VERR_SIDR_Pos (0U) -#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */ -#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk +/*************** Bit definition for RCC_I2C12CKSELR register ****************/ +#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U) +#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*!< I2C1 and I2C2 kernel clock source selection */ +#define RCC_I2C12CKSELR_I2C12SRC_0 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C12CKSELR_I2C12SRC_1 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C12CKSELR_I2C12SRC_2 (0x4U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_I2C35CKSELR register ****************/ +#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U) +#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */ +#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*!< I2C3 and I2C5 kernel clock source selection */ +#define RCC_I2C35CKSELR_I2C35SRC_0 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */ +#define RCC_I2C35CKSELR_I2C35SRC_1 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */ +#define RCC_I2C35CKSELR_I2C35SRC_2 (0x4U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI1CKSELR register ****************/ +#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U) +#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*!< SAI1 and DFSDM kernel clock source selection */ +#define RCC_SAI1CKSELR_SAI1SRC_0 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI1CKSELR_SAI1SRC_1 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI1CKSELR_SAI1SRC_2 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI2CKSELR register ****************/ +#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U) +#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*!< SAI2 kernel clock source selection */ +#define RCC_SAI2CKSELR_SAI2SRC_0 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI2CKSELR_SAI2SRC_1 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI2CKSELR_SAI2SRC_2 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI3CKSELR register ****************/ +#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U) +#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*!< SAI3 kernel clock source selection */ +#define RCC_SAI3CKSELR_SAI3SRC_0 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI3CKSELR_SAI3SRC_1 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI3CKSELR_SAI3SRC_2 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_SAI4CKSELR register ****************/ +#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U) +#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */ +#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*!< SAI4 kernel clock source selection */ +#define RCC_SAI4CKSELR_SAI4SRC_0 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */ +#define RCC_SAI4CKSELR_SAI4SRC_1 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */ +#define RCC_SAI4CKSELR_SAI4SRC_2 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI2S1CKSELR register ***************/ +#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U) +#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*!< SPI/I2S1 kernel clock source selection */ +#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SPI2S23CKSELR register ***************/ +#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U) +#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*!< SPI/I2S2,3 kernel clock source selection */ +#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SPI45CKSELR register ****************/ +#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U) +#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */ +#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*!< SPI4,5 kernel clock source selection */ +#define RCC_SPI45CKSELR_SPI45SRC_0 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */ +#define RCC_SPI45CKSELR_SPI45SRC_1 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */ +#define RCC_SPI45CKSELR_SPI45SRC_2 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART6CKSELR register ****************/ +#define RCC_UART6CKSELR_UART6SRC_Pos (0U) +#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*!< USART6 kernel clock source selection */ +#define RCC_UART6CKSELR_UART6SRC_0 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART6CKSELR_UART6SRC_1 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART6CKSELR_UART6SRC_2 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART24CKSELR register ***************/ +#define RCC_UART24CKSELR_UART24SRC_Pos (0U) +#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*!< USART2 and UART4 kernel clock source selection */ +#define RCC_UART24CKSELR_UART24SRC_0 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART24CKSELR_UART24SRC_1 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART24CKSELR_UART24SRC_2 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART35CKSELR register ***************/ +#define RCC_UART35CKSELR_UART35SRC_Pos (0U) +#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*!< USART3 and UART5 kernel clock source selection */ +#define RCC_UART35CKSELR_UART35SRC_0 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART35CKSELR_UART35SRC_1 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART35CKSELR_UART35SRC_2 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_UART78CKSELR register ***************/ +#define RCC_UART78CKSELR_UART78SRC_Pos (0U) +#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */ +#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*!< UART7 and UART8 kernel clock source selection */ +#define RCC_UART78CKSELR_UART78SRC_0 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */ +#define RCC_UART78CKSELR_UART78SRC_1 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */ +#define RCC_UART78CKSELR_UART78SRC_2 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_SDMMC12CKSELR register ***************/ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x7U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*!< SDMMC1 and SDMMC2 kernel clock source selection */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x4U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_SDMMC3CKSELR register ***************/ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x7U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000007 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*!< SDMMC3 kernel clock source selection */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x4U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000004 */ + +/**************** Bit definition for RCC_ETHCKSELR register *****************/ +#define RCC_ETHCKSELR_ETHSRC_Pos (0U) +#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */ +#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*!< ETH kernel clock source selection */ +#define RCC_ETHCKSELR_ETHSRC_0 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */ +#define RCC_ETHCKSELR_ETHSRC_1 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */ +#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U) +#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */ +#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*!< Clock divider for Ethernet Precision Time Protocol (PTP) */ +#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */ +#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */ +#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */ +#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */ + +/**************** Bit definition for RCC_QSPICKSELR register ****************/ +#define RCC_QSPICKSELR_QSPISRC_Pos (0U) +#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */ +#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*!< QUADSPI kernel clock source selection */ +#define RCC_QSPICKSELR_QSPISRC_0 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */ +#define RCC_QSPICKSELR_QSPISRC_1 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_FMCCKSELR register *****************/ +#define RCC_FMCCKSELR_FMCSRC_Pos (0U) +#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */ +#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*!< FMC kernel clock source selection */ +#define RCC_FMCCKSELR_FMCSRC_0 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */ +#define RCC_FMCCKSELR_FMCSRC_1 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_FDCANCKSELR register ****************/ +#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U) +#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */ +#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*!< FDCAN kernel clock source selection */ +#define RCC_FDCANCKSELR_FDCANSRC_0 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */ +#define RCC_FDCANCKSELR_FDCANSRC_1 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */ + +/*************** Bit definition for RCC_SPDIFCKSELR register ****************/ +#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U) +#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */ +#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*!< SPDIFRX kernel clock source selection */ +#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */ +#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_CECCKSELR register *****************/ +#define RCC_CECCKSELR_CECSRC_Pos (0U) +#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */ +#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock source selection */ +#define RCC_CECCKSELR_CECSRC_0 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */ +#define RCC_CECCKSELR_CECSRC_1 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_USBCKSELR register *****************/ +#define RCC_USBCKSELR_USBPHYSRC_Pos (0U) +#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */ +#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*!< USB PHY kernel clock source selection */ +#define RCC_USBCKSELR_USBPHYSRC_0 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */ +#define RCC_USBCKSELR_USBPHYSRC_1 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */ +#define RCC_USBCKSELR_USBOSRC_Pos (4U) +#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */ +#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*!< USB OTG kernel clock source selection */ + +/**************** Bit definition for RCC_RNG2CKSELR register ****************/ +#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U) +#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */ +#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*!< RNG2 kernel clock source selection */ +#define RCC_RNG2CKSELR_RNG2SRC_0 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */ +#define RCC_RNG2CKSELR_RNG2SRC_1 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */ + +/**************** Bit definition for RCC_DSICKSELR register *****************/ +#define RCC_DSICKSELR_DSISRC_Pos (0U) +#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */ +#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*!< DSI kernel clock source selection */ + +/**************** Bit definition for RCC_ADCCKSELR register *****************/ +#define RCC_ADCCKSELR_ADCSRC_Pos (0U) +#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */ +#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*!< ADC1&2 kernel clock source selection */ +#define RCC_ADCCKSELR_ADCSRC_0 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */ +#define RCC_ADCCKSELR_ADCSRC_1 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */ + +/************** Bit definition for RCC_LPTIM45CKSELR register ***************/ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*!< LPTIM4 and LPTIM5 kernel clock source selection */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */ + +/************** Bit definition for RCC_LPTIM23CKSELR register ***************/ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*!< LPTIM2 and LPTIM3 kernel clock source selection */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_LPTIM1CKSELR register ***************/ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*!< LPTIM1 kernel clock source selection */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */ + +/*************** Bit definition for RCC_APB1RSTSETR register ****************/ +#define RCC_APB1RSTSETR_TIM2RST_Pos (0U) +#define RCC_APB1RSTSETR_TIM2RST_Msk (0x1U << RCC_APB1RSTSETR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTSETR_TIM2RST RCC_APB1RSTSETR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTSETR_TIM3RST_Pos (1U) +#define RCC_APB1RSTSETR_TIM3RST_Msk (0x1U << RCC_APB1RSTSETR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTSETR_TIM3RST RCC_APB1RSTSETR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTSETR_TIM4RST_Pos (2U) +#define RCC_APB1RSTSETR_TIM4RST_Msk (0x1U << RCC_APB1RSTSETR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTSETR_TIM4RST RCC_APB1RSTSETR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTSETR_TIM5RST_Pos (3U) +#define RCC_APB1RSTSETR_TIM5RST_Msk (0x1U << RCC_APB1RSTSETR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTSETR_TIM5RST RCC_APB1RSTSETR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTSETR_TIM6RST_Pos (4U) +#define RCC_APB1RSTSETR_TIM6RST_Msk (0x1U << RCC_APB1RSTSETR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTSETR_TIM6RST RCC_APB1RSTSETR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTSETR_TIM7RST_Pos (5U) +#define RCC_APB1RSTSETR_TIM7RST_Msk (0x1U << RCC_APB1RSTSETR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTSETR_TIM7RST RCC_APB1RSTSETR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTSETR_TIM12RST_Pos (6U) +#define RCC_APB1RSTSETR_TIM12RST_Msk (0x1U << RCC_APB1RSTSETR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTSETR_TIM12RST RCC_APB1RSTSETR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTSETR_TIM13RST_Pos (7U) +#define RCC_APB1RSTSETR_TIM13RST_Msk (0x1U << RCC_APB1RSTSETR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTSETR_TIM13RST RCC_APB1RSTSETR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTSETR_TIM14RST_Pos (8U) +#define RCC_APB1RSTSETR_TIM14RST_Msk (0x1U << RCC_APB1RSTSETR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTSETR_TIM14RST RCC_APB1RSTSETR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTSETR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTSETR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTSETR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTSETR_LPTIM1RST RCC_APB1RSTSETR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTSETR_SPI2RST_Pos (11U) +#define RCC_APB1RSTSETR_SPI2RST_Msk (0x1U << RCC_APB1RSTSETR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTSETR_SPI2RST RCC_APB1RSTSETR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTSETR_SPI3RST_Pos (12U) +#define RCC_APB1RSTSETR_SPI3RST_Msk (0x1U << RCC_APB1RSTSETR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTSETR_SPI3RST RCC_APB1RSTSETR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTSETR_USART2RST_Pos (14U) +#define RCC_APB1RSTSETR_USART2RST_Msk (0x1U << RCC_APB1RSTSETR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTSETR_USART2RST RCC_APB1RSTSETR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTSETR_USART3RST_Pos (15U) +#define RCC_APB1RSTSETR_USART3RST_Msk (0x1U << RCC_APB1RSTSETR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTSETR_USART3RST RCC_APB1RSTSETR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTSETR_UART4RST_Pos (16U) +#define RCC_APB1RSTSETR_UART4RST_Msk (0x1U << RCC_APB1RSTSETR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTSETR_UART4RST RCC_APB1RSTSETR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTSETR_UART5RST_Pos (17U) +#define RCC_APB1RSTSETR_UART5RST_Msk (0x1U << RCC_APB1RSTSETR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTSETR_UART5RST RCC_APB1RSTSETR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTSETR_UART7RST_Pos (18U) +#define RCC_APB1RSTSETR_UART7RST_Msk (0x1U << RCC_APB1RSTSETR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTSETR_UART7RST RCC_APB1RSTSETR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTSETR_UART8RST_Pos (19U) +#define RCC_APB1RSTSETR_UART8RST_Msk (0x1U << RCC_APB1RSTSETR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTSETR_UART8RST RCC_APB1RSTSETR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTSETR_I2C1RST_Pos (21U) +#define RCC_APB1RSTSETR_I2C1RST_Msk (0x1U << RCC_APB1RSTSETR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTSETR_I2C1RST RCC_APB1RSTSETR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTSETR_I2C2RST_Pos (22U) +#define RCC_APB1RSTSETR_I2C2RST_Msk (0x1U << RCC_APB1RSTSETR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTSETR_I2C2RST RCC_APB1RSTSETR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTSETR_I2C3RST_Pos (23U) +#define RCC_APB1RSTSETR_I2C3RST_Msk (0x1U << RCC_APB1RSTSETR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTSETR_I2C3RST RCC_APB1RSTSETR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTSETR_I2C5RST_Pos (24U) +#define RCC_APB1RSTSETR_I2C5RST_Msk (0x1U << RCC_APB1RSTSETR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTSETR_I2C5RST RCC_APB1RSTSETR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTSETR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTSETR_SPDIFRST_Msk (0x1U << RCC_APB1RSTSETR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTSETR_SPDIFRST RCC_APB1RSTSETR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTSETR_CECRST_Pos (27U) +#define RCC_APB1RSTSETR_CECRST_Msk (0x1U << RCC_APB1RSTSETR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTSETR_CECRST RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTSETR_DAC12RST_Pos (29U) +#define RCC_APB1RSTSETR_DAC12RST_Msk (0x1U << RCC_APB1RSTSETR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTSETR_DAC12RST RCC_APB1RSTSETR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTSETR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTSETR_MDIOSRST_Msk (0x1U << RCC_APB1RSTSETR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTSETR_MDIOSRST RCC_APB1RSTSETR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB1RSTCLRR register ****************/ +#define RCC_APB1RSTCLRR_TIM2RST_Pos (0U) +#define RCC_APB1RSTCLRR_TIM2RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTCLRR_TIM2RST RCC_APB1RSTCLRR_TIM2RST_Msk /*!< TIM2 block reset */ +#define RCC_APB1RSTCLRR_TIM3RST_Pos (1U) +#define RCC_APB1RSTCLRR_TIM3RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTCLRR_TIM3RST RCC_APB1RSTCLRR_TIM3RST_Msk /*!< TIM3 block reset */ +#define RCC_APB1RSTCLRR_TIM4RST_Pos (2U) +#define RCC_APB1RSTCLRR_TIM4RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTCLRR_TIM4RST RCC_APB1RSTCLRR_TIM4RST_Msk /*!< TIM4 block reset */ +#define RCC_APB1RSTCLRR_TIM5RST_Pos (3U) +#define RCC_APB1RSTCLRR_TIM5RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTCLRR_TIM5RST RCC_APB1RSTCLRR_TIM5RST_Msk /*!< TIM5 block reset */ +#define RCC_APB1RSTCLRR_TIM6RST_Pos (4U) +#define RCC_APB1RSTCLRR_TIM6RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTCLRR_TIM6RST RCC_APB1RSTCLRR_TIM6RST_Msk /*!< TIM6 block reset */ +#define RCC_APB1RSTCLRR_TIM7RST_Pos (5U) +#define RCC_APB1RSTCLRR_TIM7RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTCLRR_TIM7RST RCC_APB1RSTCLRR_TIM7RST_Msk /*!< TIM7 block reset */ +#define RCC_APB1RSTCLRR_TIM12RST_Pos (6U) +#define RCC_APB1RSTCLRR_TIM12RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTCLRR_TIM12RST RCC_APB1RSTCLRR_TIM12RST_Msk /*!< TIM12 block reset */ +#define RCC_APB1RSTCLRR_TIM13RST_Pos (7U) +#define RCC_APB1RSTCLRR_TIM13RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTCLRR_TIM13RST RCC_APB1RSTCLRR_TIM13RST_Msk /*!< TIM13 block reset */ +#define RCC_APB1RSTCLRR_TIM14RST_Pos (8U) +#define RCC_APB1RSTCLRR_TIM14RST_Msk (0x1U << RCC_APB1RSTCLRR_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTCLRR_TIM14RST RCC_APB1RSTCLRR_TIM14RST_Msk /*!< TIM14 block reset */ +#define RCC_APB1RSTCLRR_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTCLRR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTCLRR_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTCLRR_LPTIM1RST RCC_APB1RSTCLRR_LPTIM1RST_Msk /*!< LPTIM1 block reset */ +#define RCC_APB1RSTCLRR_SPI2RST_Pos (11U) +#define RCC_APB1RSTCLRR_SPI2RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI2RST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTCLRR_SPI2RST RCC_APB1RSTCLRR_SPI2RST_Msk /*!< SPI2 block reset */ +#define RCC_APB1RSTCLRR_SPI3RST_Pos (12U) +#define RCC_APB1RSTCLRR_SPI3RST_Msk (0x1U << RCC_APB1RSTCLRR_SPI3RST_Pos) /*!< 0x00001000 */ +#define RCC_APB1RSTCLRR_SPI3RST RCC_APB1RSTCLRR_SPI3RST_Msk /*!< SPI3 block reset */ +#define RCC_APB1RSTCLRR_USART2RST_Pos (14U) +#define RCC_APB1RSTCLRR_USART2RST_Msk (0x1U << RCC_APB1RSTCLRR_USART2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTCLRR_USART2RST RCC_APB1RSTCLRR_USART2RST_Msk /*!< USART2 block reset */ +#define RCC_APB1RSTCLRR_USART3RST_Pos (15U) +#define RCC_APB1RSTCLRR_USART3RST_Msk (0x1U << RCC_APB1RSTCLRR_USART3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTCLRR_USART3RST RCC_APB1RSTCLRR_USART3RST_Msk /*!< USART3 block reset */ +#define RCC_APB1RSTCLRR_UART4RST_Pos (16U) +#define RCC_APB1RSTCLRR_UART4RST_Msk (0x1U << RCC_APB1RSTCLRR_UART4RST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTCLRR_UART4RST RCC_APB1RSTCLRR_UART4RST_Msk /*!< UART4 block reset */ +#define RCC_APB1RSTCLRR_UART5RST_Pos (17U) +#define RCC_APB1RSTCLRR_UART5RST_Msk (0x1U << RCC_APB1RSTCLRR_UART5RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTCLRR_UART5RST RCC_APB1RSTCLRR_UART5RST_Msk /*!< UART5 block reset */ +#define RCC_APB1RSTCLRR_UART7RST_Pos (18U) +#define RCC_APB1RSTCLRR_UART7RST_Msk (0x1U << RCC_APB1RSTCLRR_UART7RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTCLRR_UART7RST RCC_APB1RSTCLRR_UART7RST_Msk /*!< UART7 block reset */ +#define RCC_APB1RSTCLRR_UART8RST_Pos (19U) +#define RCC_APB1RSTCLRR_UART8RST_Msk (0x1U << RCC_APB1RSTCLRR_UART8RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTCLRR_UART8RST RCC_APB1RSTCLRR_UART8RST_Msk /*!< UART8 block reset */ +#define RCC_APB1RSTCLRR_I2C1RST_Pos (21U) +#define RCC_APB1RSTCLRR_I2C1RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTCLRR_I2C1RST RCC_APB1RSTCLRR_I2C1RST_Msk /*!< I2C1 block reset */ +#define RCC_APB1RSTCLRR_I2C2RST_Pos (22U) +#define RCC_APB1RSTCLRR_I2C2RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTCLRR_I2C2RST RCC_APB1RSTCLRR_I2C2RST_Msk /*!< I2C2 block reset */ +#define RCC_APB1RSTCLRR_I2C3RST_Pos (23U) +#define RCC_APB1RSTCLRR_I2C3RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTCLRR_I2C3RST RCC_APB1RSTCLRR_I2C3RST_Msk /*!< I2C3 block reset */ +#define RCC_APB1RSTCLRR_I2C5RST_Pos (24U) +#define RCC_APB1RSTCLRR_I2C5RST_Msk (0x1U << RCC_APB1RSTCLRR_I2C5RST_Pos) /*!< 0x01000000 */ +#define RCC_APB1RSTCLRR_I2C5RST RCC_APB1RSTCLRR_I2C5RST_Msk /*!< I2C5 block reset */ +#define RCC_APB1RSTCLRR_SPDIFRST_Pos (26U) +#define RCC_APB1RSTCLRR_SPDIFRST_Msk (0x1U << RCC_APB1RSTCLRR_SPDIFRST_Pos) /*!< 0x04000000 */ +#define RCC_APB1RSTCLRR_SPDIFRST RCC_APB1RSTCLRR_SPDIFRST_Msk /*!< SPDIFRX block reset */ +#define RCC_APB1RSTCLRR_CECRST_Pos (27U) +#define RCC_APB1RSTCLRR_CECRST_Msk (0x1U << RCC_APB1RSTCLRR_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTCLRR_CECRST RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */ +#define RCC_APB1RSTCLRR_DAC12RST_Pos (29U) +#define RCC_APB1RSTCLRR_DAC12RST_Msk (0x1U << RCC_APB1RSTCLRR_DAC12RST_Pos) /*!< 0x20000000 */ +#define RCC_APB1RSTCLRR_DAC12RST RCC_APB1RSTCLRR_DAC12RST_Msk /*!< DAC1&2 block reset */ +#define RCC_APB1RSTCLRR_MDIOSRST_Pos (31U) +#define RCC_APB1RSTCLRR_MDIOSRST_Msk (0x1U << RCC_APB1RSTCLRR_MDIOSRST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTCLRR_MDIOSRST RCC_APB1RSTCLRR_MDIOSRST_Msk /*!< MDIOS block reset */ + +/*************** Bit definition for RCC_APB2RSTSETR register ****************/ +#define RCC_APB2RSTSETR_TIM1RST_Pos (0U) +#define RCC_APB2RSTSETR_TIM1RST_Msk (0x1U << RCC_APB2RSTSETR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTSETR_TIM1RST RCC_APB2RSTSETR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTSETR_TIM8RST_Pos (1U) +#define RCC_APB2RSTSETR_TIM8RST_Msk (0x1U << RCC_APB2RSTSETR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTSETR_TIM8RST RCC_APB2RSTSETR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTSETR_TIM15RST_Pos (2U) +#define RCC_APB2RSTSETR_TIM15RST_Msk (0x1U << RCC_APB2RSTSETR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTSETR_TIM15RST RCC_APB2RSTSETR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTSETR_TIM16RST_Pos (3U) +#define RCC_APB2RSTSETR_TIM16RST_Msk (0x1U << RCC_APB2RSTSETR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTSETR_TIM16RST RCC_APB2RSTSETR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTSETR_TIM17RST_Pos (4U) +#define RCC_APB2RSTSETR_TIM17RST_Msk (0x1U << RCC_APB2RSTSETR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTSETR_TIM17RST RCC_APB2RSTSETR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTSETR_SPI1RST_Pos (8U) +#define RCC_APB2RSTSETR_SPI1RST_Msk (0x1U << RCC_APB2RSTSETR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTSETR_SPI1RST RCC_APB2RSTSETR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTSETR_SPI4RST_Pos (9U) +#define RCC_APB2RSTSETR_SPI4RST_Msk (0x1U << RCC_APB2RSTSETR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTSETR_SPI4RST RCC_APB2RSTSETR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTSETR_SPI5RST_Pos (10U) +#define RCC_APB2RSTSETR_SPI5RST_Msk (0x1U << RCC_APB2RSTSETR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTSETR_SPI5RST RCC_APB2RSTSETR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTSETR_USART6RST_Pos (13U) +#define RCC_APB2RSTSETR_USART6RST_Msk (0x1U << RCC_APB2RSTSETR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTSETR_USART6RST RCC_APB2RSTSETR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTSETR_SAI1RST_Pos (16U) +#define RCC_APB2RSTSETR_SAI1RST_Msk (0x1U << RCC_APB2RSTSETR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTSETR_SAI1RST RCC_APB2RSTSETR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTSETR_SAI2RST_Pos (17U) +#define RCC_APB2RSTSETR_SAI2RST_Msk (0x1U << RCC_APB2RSTSETR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTSETR_SAI2RST RCC_APB2RSTSETR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTSETR_SAI3RST_Pos (18U) +#define RCC_APB2RSTSETR_SAI3RST_Msk (0x1U << RCC_APB2RSTSETR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTSETR_SAI3RST RCC_APB2RSTSETR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTSETR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTSETR_DFSDMRST_Msk (0x1U << RCC_APB2RSTSETR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTSETR_DFSDMRST RCC_APB2RSTSETR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTSETR_FDCANRST_Pos (24U) +#define RCC_APB2RSTSETR_FDCANRST_Msk (0x1U << RCC_APB2RSTSETR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTSETR_FDCANRST RCC_APB2RSTSETR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB2RSTCLRR register ****************/ +#define RCC_APB2RSTCLRR_TIM1RST_Pos (0U) +#define RCC_APB2RSTCLRR_TIM1RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTCLRR_TIM1RST RCC_APB2RSTCLRR_TIM1RST_Msk /*!< TIM1 block reset */ +#define RCC_APB2RSTCLRR_TIM8RST_Pos (1U) +#define RCC_APB2RSTCLRR_TIM8RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM8RST_Pos) /*!< 0x00000002 */ +#define RCC_APB2RSTCLRR_TIM8RST RCC_APB2RSTCLRR_TIM8RST_Msk /*!< TIM8 block reset */ +#define RCC_APB2RSTCLRR_TIM15RST_Pos (2U) +#define RCC_APB2RSTCLRR_TIM15RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM15RST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTCLRR_TIM15RST RCC_APB2RSTCLRR_TIM15RST_Msk /*!< TIM15 block reset */ +#define RCC_APB2RSTCLRR_TIM16RST_Pos (3U) +#define RCC_APB2RSTCLRR_TIM16RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM16RST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTCLRR_TIM16RST RCC_APB2RSTCLRR_TIM16RST_Msk /*!< TIM16 block reset */ +#define RCC_APB2RSTCLRR_TIM17RST_Pos (4U) +#define RCC_APB2RSTCLRR_TIM17RST_Msk (0x1U << RCC_APB2RSTCLRR_TIM17RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTCLRR_TIM17RST RCC_APB2RSTCLRR_TIM17RST_Msk /*!< TIM17 block reset */ +#define RCC_APB2RSTCLRR_SPI1RST_Pos (8U) +#define RCC_APB2RSTCLRR_SPI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI1RST_Pos) /*!< 0x00000100 */ +#define RCC_APB2RSTCLRR_SPI1RST RCC_APB2RSTCLRR_SPI1RST_Msk /*!< SPI/I2S1 block reset */ +#define RCC_APB2RSTCLRR_SPI4RST_Pos (9U) +#define RCC_APB2RSTCLRR_SPI4RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI4RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTCLRR_SPI4RST RCC_APB2RSTCLRR_SPI4RST_Msk /*!< SPI4 block reset */ +#define RCC_APB2RSTCLRR_SPI5RST_Pos (10U) +#define RCC_APB2RSTCLRR_SPI5RST_Msk (0x1U << RCC_APB2RSTCLRR_SPI5RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTCLRR_SPI5RST RCC_APB2RSTCLRR_SPI5RST_Msk /*!< SPI5 block reset */ +#define RCC_APB2RSTCLRR_USART6RST_Pos (13U) +#define RCC_APB2RSTCLRR_USART6RST_Msk (0x1U << RCC_APB2RSTCLRR_USART6RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTCLRR_USART6RST RCC_APB2RSTCLRR_USART6RST_Msk /*!< USART6 block reset */ +#define RCC_APB2RSTCLRR_SAI1RST_Pos (16U) +#define RCC_APB2RSTCLRR_SAI1RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI1RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTCLRR_SAI1RST RCC_APB2RSTCLRR_SAI1RST_Msk /*!< SAI1 block reset */ +#define RCC_APB2RSTCLRR_SAI2RST_Pos (17U) +#define RCC_APB2RSTCLRR_SAI2RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTCLRR_SAI2RST RCC_APB2RSTCLRR_SAI2RST_Msk /*!< SAI2 block reset */ +#define RCC_APB2RSTCLRR_SAI3RST_Pos (18U) +#define RCC_APB2RSTCLRR_SAI3RST_Msk (0x1U << RCC_APB2RSTCLRR_SAI3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTCLRR_SAI3RST RCC_APB2RSTCLRR_SAI3RST_Msk /*!< SAI3 block reset */ +#define RCC_APB2RSTCLRR_DFSDMRST_Pos (20U) +#define RCC_APB2RSTCLRR_DFSDMRST_Msk (0x1U << RCC_APB2RSTCLRR_DFSDMRST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTCLRR_DFSDMRST RCC_APB2RSTCLRR_DFSDMRST_Msk /*!< DFSDM block reset */ +#define RCC_APB2RSTCLRR_FDCANRST_Pos (24U) +#define RCC_APB2RSTCLRR_FDCANRST_Msk (0x1U << RCC_APB2RSTCLRR_FDCANRST_Pos) /*!< 0x01000000 */ +#define RCC_APB2RSTCLRR_FDCANRST RCC_APB2RSTCLRR_FDCANRST_Msk /*!< FDCAN block reset */ + +/*************** Bit definition for RCC_APB3RSTSETR register ****************/ +#define RCC_APB3RSTSETR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTSETR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTSETR_LPTIM2RST RCC_APB3RSTSETR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTSETR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTSETR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTSETR_LPTIM3RST RCC_APB3RSTSETR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTSETR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTSETR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTSETR_LPTIM4RST RCC_APB3RSTSETR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTSETR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTSETR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTSETR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTSETR_LPTIM5RST RCC_APB3RSTSETR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTSETR_SAI4RST_Pos (8U) +#define RCC_APB3RSTSETR_SAI4RST_Msk (0x1U << RCC_APB3RSTSETR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTSETR_SAI4RST RCC_APB3RSTSETR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTSETR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTSETR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTSETR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTSETR_SYSCFGRST RCC_APB3RSTSETR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTSETR_VREFRST_Pos (13U) +#define RCC_APB3RSTSETR_VREFRST_Msk (0x1U << RCC_APB3RSTSETR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTSETR_VREFRST RCC_APB3RSTSETR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTSETR_DTSRST_Pos (16U) +#define RCC_APB3RSTSETR_DTSRST_Msk (0x1U << RCC_APB3RSTSETR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTSETR_DTSRST RCC_APB3RSTSETR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_APB3RSTCLRR register ****************/ +#define RCC_APB3RSTCLRR_LPTIM2RST_Pos (0U) +#define RCC_APB3RSTCLRR_LPTIM2RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB3RSTCLRR_LPTIM2RST RCC_APB3RSTCLRR_LPTIM2RST_Msk /*!< LPTIM2 block reset */ +#define RCC_APB3RSTCLRR_LPTIM3RST_Pos (1U) +#define RCC_APB3RSTCLRR_LPTIM3RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB3RSTCLRR_LPTIM3RST RCC_APB3RSTCLRR_LPTIM3RST_Msk /*!< LPTIM3 block reset */ +#define RCC_APB3RSTCLRR_LPTIM4RST_Pos (2U) +#define RCC_APB3RSTCLRR_LPTIM4RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB3RSTCLRR_LPTIM4RST RCC_APB3RSTCLRR_LPTIM4RST_Msk /*!< LPTIM4 block reset */ +#define RCC_APB3RSTCLRR_LPTIM5RST_Pos (3U) +#define RCC_APB3RSTCLRR_LPTIM5RST_Msk (0x1U << RCC_APB3RSTCLRR_LPTIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB3RSTCLRR_LPTIM5RST RCC_APB3RSTCLRR_LPTIM5RST_Msk /*!< LPTIM5 block reset */ +#define RCC_APB3RSTCLRR_SAI4RST_Pos (8U) +#define RCC_APB3RSTCLRR_SAI4RST_Msk (0x1U << RCC_APB3RSTCLRR_SAI4RST_Pos) /*!< 0x00000100 */ +#define RCC_APB3RSTCLRR_SAI4RST RCC_APB3RSTCLRR_SAI4RST_Msk /*!< SAI4 block reset */ +#define RCC_APB3RSTCLRR_SYSCFGRST_Pos (11U) +#define RCC_APB3RSTCLRR_SYSCFGRST_Msk (0x1U << RCC_APB3RSTCLRR_SYSCFGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB3RSTCLRR_SYSCFGRST RCC_APB3RSTCLRR_SYSCFGRST_Msk /*!< SYSCFG block reset */ +#define RCC_APB3RSTCLRR_VREFRST_Pos (13U) +#define RCC_APB3RSTCLRR_VREFRST_Msk (0x1U << RCC_APB3RSTCLRR_VREFRST_Pos) /*!< 0x00002000 */ +#define RCC_APB3RSTCLRR_VREFRST RCC_APB3RSTCLRR_VREFRST_Msk /*!< VREF block reset */ +#define RCC_APB3RSTCLRR_DTSRST_Pos (16U) +#define RCC_APB3RSTCLRR_DTSRST_Msk (0x1U << RCC_APB3RSTCLRR_DTSRST_Pos) /*!< 0x00010000 */ +#define RCC_APB3RSTCLRR_DTSRST RCC_APB3RSTCLRR_DTSRST_Msk /*!< DTS block reset */ + +/*************** Bit definition for RCC_AHB2RSTSETR register ****************/ +#define RCC_AHB2RSTSETR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTSETR_DMA1RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTSETR_DMA1RST RCC_AHB2RSTSETR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTSETR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTSETR_DMA2RST_Msk (0x1U << RCC_AHB2RSTSETR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTSETR_DMA2RST RCC_AHB2RSTSETR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTSETR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTSETR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTSETR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTSETR_DMAMUXRST RCC_AHB2RSTSETR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTSETR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTSETR_ADC12RST_Msk (0x1U << RCC_AHB2RSTSETR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTSETR_ADC12RST RCC_AHB2RSTSETR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTSETR_USBORST_Pos (8U) +#define RCC_AHB2RSTSETR_USBORST_Msk (0x1U << RCC_AHB2RSTSETR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTSETR_USBORST RCC_AHB2RSTSETR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTSETR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTSETR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTSETR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTSETR_SDMMC3RST RCC_AHB2RSTSETR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB2RSTCLRR register ****************/ +#define RCC_AHB2RSTCLRR_DMA1RST_Pos (0U) +#define RCC_AHB2RSTCLRR_DMA1RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTCLRR_DMA1RST RCC_AHB2RSTCLRR_DMA1RST_Msk /*!< DMA1 block reset */ +#define RCC_AHB2RSTCLRR_DMA2RST_Pos (1U) +#define RCC_AHB2RSTCLRR_DMA2RST_Msk (0x1U << RCC_AHB2RSTCLRR_DMA2RST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTCLRR_DMA2RST RCC_AHB2RSTCLRR_DMA2RST_Msk /*!< DMA2 block reset */ +#define RCC_AHB2RSTCLRR_DMAMUXRST_Pos (2U) +#define RCC_AHB2RSTCLRR_DMAMUXRST_Msk (0x1U << RCC_AHB2RSTCLRR_DMAMUXRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTCLRR_DMAMUXRST RCC_AHB2RSTCLRR_DMAMUXRST_Msk /*!< DMAMUX block reset */ +#define RCC_AHB2RSTCLRR_ADC12RST_Pos (5U) +#define RCC_AHB2RSTCLRR_ADC12RST_Msk (0x1U << RCC_AHB2RSTCLRR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB2RSTCLRR_ADC12RST RCC_AHB2RSTCLRR_ADC12RST_Msk /*!< ADC1&2 block reset */ +#define RCC_AHB2RSTCLRR_USBORST_Pos (8U) +#define RCC_AHB2RSTCLRR_USBORST_Msk (0x1U << RCC_AHB2RSTCLRR_USBORST_Pos) /*!< 0x00000100 */ +#define RCC_AHB2RSTCLRR_USBORST RCC_AHB2RSTCLRR_USBORST_Msk /*!< USBO block reset */ +#define RCC_AHB2RSTCLRR_SDMMC3RST_Pos (16U) +#define RCC_AHB2RSTCLRR_SDMMC3RST_Msk (0x1U << RCC_AHB2RSTCLRR_SDMMC3RST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTCLRR_SDMMC3RST RCC_AHB2RSTCLRR_SDMMC3RST_Msk /*!< SDMMC3 and the SDMMC3 delay (DLYBSD3) block reset */ + +/*************** Bit definition for RCC_AHB3RSTSETR register ****************/ +#define RCC_AHB3RSTSETR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTSETR_DCMIRST_Msk (0x1U << RCC_AHB3RSTSETR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTSETR_DCMIRST RCC_AHB3RSTSETR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTSETR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTSETR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTSETR_CRYP2RST RCC_AHB3RSTSETR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTSETR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTSETR_HASH2RST_Msk (0x1U << RCC_AHB3RSTSETR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTSETR_HASH2RST RCC_AHB3RSTSETR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTSETR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTSETR_RNG2RST_Msk (0x1U << RCC_AHB3RSTSETR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTSETR_RNG2RST RCC_AHB3RSTSETR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTSETR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTSETR_CRC2RST_Msk (0x1U << RCC_AHB3RSTSETR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTSETR_CRC2RST RCC_AHB3RSTSETR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTSETR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTSETR_HSEMRST_Msk (0x1U << RCC_AHB3RSTSETR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTSETR_HSEMRST RCC_AHB3RSTSETR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTSETR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTSETR_IPCCRST_Msk (0x1U << RCC_AHB3RSTSETR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTSETR_IPCCRST RCC_AHB3RSTSETR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB3RSTCLRR register ****************/ +#define RCC_AHB3RSTCLRR_DCMIRST_Pos (0U) +#define RCC_AHB3RSTCLRR_DCMIRST_Msk (0x1U << RCC_AHB3RSTCLRR_DCMIRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTCLRR_DCMIRST RCC_AHB3RSTCLRR_DCMIRST_Msk /*!< DCMI block reset */ +#define RCC_AHB3RSTCLRR_CRYP2RST_Pos (4U) +#define RCC_AHB3RSTCLRR_CRYP2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRYP2RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTCLRR_CRYP2RST RCC_AHB3RSTCLRR_CRYP2RST_Msk /*!< CRYP2 (3DES/AES2) block reset */ +#define RCC_AHB3RSTCLRR_HASH2RST_Pos (5U) +#define RCC_AHB3RSTCLRR_HASH2RST_Msk (0x1U << RCC_AHB3RSTCLRR_HASH2RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB3RSTCLRR_HASH2RST RCC_AHB3RSTCLRR_HASH2RST_Msk /*!< HASH2 block reset */ +#define RCC_AHB3RSTCLRR_RNG2RST_Pos (6U) +#define RCC_AHB3RSTCLRR_RNG2RST_Msk (0x1U << RCC_AHB3RSTCLRR_RNG2RST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTCLRR_RNG2RST RCC_AHB3RSTCLRR_RNG2RST_Msk /*!< RNG2 block reset */ +#define RCC_AHB3RSTCLRR_CRC2RST_Pos (7U) +#define RCC_AHB3RSTCLRR_CRC2RST_Msk (0x1U << RCC_AHB3RSTCLRR_CRC2RST_Pos) /*!< 0x00000080 */ +#define RCC_AHB3RSTCLRR_CRC2RST RCC_AHB3RSTCLRR_CRC2RST_Msk /*!< CRC2 block reset */ +#define RCC_AHB3RSTCLRR_HSEMRST_Pos (11U) +#define RCC_AHB3RSTCLRR_HSEMRST_Msk (0x1U << RCC_AHB3RSTCLRR_HSEMRST_Pos) /*!< 0x00000800 */ +#define RCC_AHB3RSTCLRR_HSEMRST RCC_AHB3RSTCLRR_HSEMRST_Msk /*!< HSEM block reset */ +#define RCC_AHB3RSTCLRR_IPCCRST_Pos (12U) +#define RCC_AHB3RSTCLRR_IPCCRST_Msk (0x1U << RCC_AHB3RSTCLRR_IPCCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB3RSTCLRR_IPCCRST RCC_AHB3RSTCLRR_IPCCRST_Msk /*!< IPCC block reset */ + +/*************** Bit definition for RCC_AHB4RSTSETR register ****************/ +#define RCC_AHB4RSTSETR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTSETR_GPIOARST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTSETR_GPIOARST RCC_AHB4RSTSETR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTSETR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTSETR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTSETR_GPIOBRST RCC_AHB4RSTSETR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTSETR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTSETR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTSETR_GPIOCRST RCC_AHB4RSTSETR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTSETR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTSETR_GPIODRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTSETR_GPIODRST RCC_AHB4RSTSETR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTSETR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTSETR_GPIOERST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTSETR_GPIOERST RCC_AHB4RSTSETR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTSETR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTSETR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTSETR_GPIOFRST RCC_AHB4RSTSETR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTSETR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTSETR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTSETR_GPIOGRST RCC_AHB4RSTSETR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTSETR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTSETR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTSETR_GPIOHRST RCC_AHB4RSTSETR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTSETR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTSETR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTSETR_GPIOIRST RCC_AHB4RSTSETR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTSETR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTSETR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTSETR_GPIOJRST RCC_AHB4RSTSETR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTSETR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTSETR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTSETR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTSETR_GPIOKRST RCC_AHB4RSTSETR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/*************** Bit definition for RCC_AHB4RSTCLRR register ****************/ +#define RCC_AHB4RSTCLRR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTCLRR_GPIOARST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTCLRR_GPIOARST RCC_AHB4RSTCLRR_GPIOARST_Msk /*!< GPIOA block reset */ +#define RCC_AHB4RSTCLRR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTCLRR_GPIOBRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTCLRR_GPIOBRST RCC_AHB4RSTCLRR_GPIOBRST_Msk /*!< GPIOB block reset */ +#define RCC_AHB4RSTCLRR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTCLRR_GPIOCRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTCLRR_GPIOCRST RCC_AHB4RSTCLRR_GPIOCRST_Msk /*!< GPIOC block reset */ +#define RCC_AHB4RSTCLRR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTCLRR_GPIODRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTCLRR_GPIODRST RCC_AHB4RSTCLRR_GPIODRST_Msk /*!< GPIOD block reset */ +#define RCC_AHB4RSTCLRR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTCLRR_GPIOERST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTCLRR_GPIOERST RCC_AHB4RSTCLRR_GPIOERST_Msk /*!< GPIOE block reset */ +#define RCC_AHB4RSTCLRR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTCLRR_GPIOFRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTCLRR_GPIOFRST RCC_AHB4RSTCLRR_GPIOFRST_Msk /*!< GPIOF block reset */ +#define RCC_AHB4RSTCLRR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTCLRR_GPIOGRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTCLRR_GPIOGRST RCC_AHB4RSTCLRR_GPIOGRST_Msk /*!< GPIOG block reset */ +#define RCC_AHB4RSTCLRR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTCLRR_GPIOHRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTCLRR_GPIOHRST RCC_AHB4RSTCLRR_GPIOHRST_Msk /*!< GPIOH block reset */ +#define RCC_AHB4RSTCLRR_GPIOIRST_Pos (8U) +#define RCC_AHB4RSTCLRR_GPIOIRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOIRST_Pos) /*!< 0x00000100 */ +#define RCC_AHB4RSTCLRR_GPIOIRST RCC_AHB4RSTCLRR_GPIOIRST_Msk /*!< GPIOI block reset */ +#define RCC_AHB4RSTCLRR_GPIOJRST_Pos (9U) +#define RCC_AHB4RSTCLRR_GPIOJRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOJRST_Pos) /*!< 0x00000200 */ +#define RCC_AHB4RSTCLRR_GPIOJRST RCC_AHB4RSTCLRR_GPIOJRST_Msk /*!< GPIOJ block reset */ +#define RCC_AHB4RSTCLRR_GPIOKRST_Pos (10U) +#define RCC_AHB4RSTCLRR_GPIOKRST_Msk (0x1U << RCC_AHB4RSTCLRR_GPIOKRST_Pos) /*!< 0x00000400 */ +#define RCC_AHB4RSTCLRR_GPIOKRST RCC_AHB4RSTCLRR_GPIOKRST_Msk /*!< GPIOK block reset */ + +/************** Bit definition for RCC_MP_APB1ENSETR register ***************/ +#define RCC_MP_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENSETR_TIM2EN RCC_MP_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENSETR_TIM3EN RCC_MP_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENSETR_TIM4EN RCC_MP_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENSETR_TIM5EN RCC_MP_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENSETR_TIM6EN RCC_MP_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENSETR_TIM7EN RCC_MP_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENSETR_TIM12EN RCC_MP_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENSETR_TIM13EN RCC_MP_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENSETR_TIM14EN RCC_MP_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENSETR_LPTIM1EN RCC_MP_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENSETR_SPI2EN RCC_MP_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENSETR_SPI3EN RCC_MP_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENSETR_USART2EN RCC_MP_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MP_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENSETR_USART3EN RCC_MP_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENSETR_UART4EN RCC_MP_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENSETR_UART5EN RCC_MP_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENSETR_UART7EN RCC_MP_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MP_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENSETR_UART8EN RCC_MP_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENSETR_I2C1EN RCC_MP_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENSETR_I2C2EN RCC_MP_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENSETR_I2C3EN RCC_MP_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENSETR_I2C5EN RCC_MP_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENSETR_SPDIFEN RCC_MP_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MP_APB1ENSETR_CECEN_Msk (0x1U << RCC_MP_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENSETR_CECEN RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENSETR_DAC12EN RCC_MP_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENSETR_MDIOSEN RCC_MP_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB1ENCLRR register ***************/ +#define RCC_MP_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MP_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1ENCLRR_TIM2EN RCC_MP_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MP_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1ENCLRR_TIM3EN RCC_MP_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MP_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1ENCLRR_TIM4EN RCC_MP_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MP_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1ENCLRR_TIM5EN RCC_MP_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MP_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1ENCLRR_TIM6EN RCC_MP_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MP_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1ENCLRR_TIM7EN RCC_MP_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MP_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1ENCLRR_TIM12EN RCC_MP_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MP_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1ENCLRR_TIM13EN RCC_MP_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MP_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MP_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1ENCLRR_TIM14EN RCC_MP_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MP_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1ENCLRR_LPTIM1EN RCC_MP_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MP_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1ENCLRR_SPI2EN RCC_MP_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MP_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1ENCLRR_SPI3EN RCC_MP_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MP_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1ENCLRR_USART2EN RCC_MP_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MP_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1ENCLRR_USART3EN RCC_MP_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MP_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1ENCLRR_UART4EN RCC_MP_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MP_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1ENCLRR_UART5EN RCC_MP_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MP_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1ENCLRR_UART7EN RCC_MP_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MP_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MP_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1ENCLRR_UART8EN RCC_MP_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MP_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1ENCLRR_I2C1EN RCC_MP_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MP_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1ENCLRR_I2C2EN RCC_MP_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MP_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1ENCLRR_I2C3EN RCC_MP_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MP_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MP_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1ENCLRR_I2C5EN RCC_MP_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MP_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MP_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1ENCLRR_SPDIFEN RCC_MP_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MP_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MP_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1ENCLRR_CECEN RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MP_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MP_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1ENCLRR_DAC12EN RCC_MP_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MP_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MP_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MP_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1ENCLRR_MDIOSEN RCC_MP_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENSETR register ***************/ +#define RCC_MP_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENSETR_TIM1EN RCC_MP_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENSETR_TIM8EN RCC_MP_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENSETR_TIM15EN RCC_MP_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENSETR_TIM16EN RCC_MP_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENSETR_TIM17EN RCC_MP_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENSETR_SPI1EN RCC_MP_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENSETR_SPI4EN RCC_MP_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENSETR_SPI5EN RCC_MP_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MP_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENSETR_USART6EN RCC_MP_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENSETR_SAI1EN RCC_MP_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENSETR_SAI2EN RCC_MP_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENSETR_SAI3EN RCC_MP_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENSETR_DFSDMEN RCC_MP_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENSETR_ADFSDMEN RCC_MP_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENSETR_FDCANEN RCC_MP_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB2ENCLRR register ***************/ +#define RCC_MP_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MP_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2ENCLRR_TIM1EN RCC_MP_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MP_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2ENCLRR_TIM8EN RCC_MP_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MP_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2ENCLRR_TIM15EN RCC_MP_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MP_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2ENCLRR_TIM16EN RCC_MP_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MP_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MP_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2ENCLRR_TIM17EN RCC_MP_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MP_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2ENCLRR_SPI1EN RCC_MP_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MP_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2ENCLRR_SPI4EN RCC_MP_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MP_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2ENCLRR_SPI5EN RCC_MP_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MP_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MP_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2ENCLRR_USART6EN RCC_MP_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MP_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2ENCLRR_SAI1EN RCC_MP_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MP_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2ENCLRR_SAI2EN RCC_MP_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MP_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MP_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2ENCLRR_SAI3EN RCC_MP_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MP_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2ENCLRR_DFSDMEN RCC_MP_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MP_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MP_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2ENCLRR_ADFSDMEN RCC_MP_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MP_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MP_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MP_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2ENCLRR_FDCANEN RCC_MP_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENSETR register ***************/ +#define RCC_MP_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENSETR_LPTIM2EN RCC_MP_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENSETR_LPTIM3EN RCC_MP_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENSETR_LPTIM4EN RCC_MP_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENSETR_LPTIM5EN RCC_MP_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENSETR_SAI4EN RCC_MP_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENSETR_SYSCFGEN RCC_MP_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MP_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENSETR_VREFEN RCC_MP_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MP_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENSETR_DTSEN RCC_MP_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MP_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENSETR_HDPEN RCC_MP_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_APB3ENCLRR register ***************/ +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MP_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN RCC_MP_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MP_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3ENCLRR_LPTIM3EN RCC_MP_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MP_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3ENCLRR_LPTIM4EN RCC_MP_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MP_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MP_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3ENCLRR_LPTIM5EN RCC_MP_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MP_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MP_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3ENCLRR_SAI4EN RCC_MP_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MP_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MP_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3ENCLRR_SYSCFGEN RCC_MP_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MP_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MP_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3ENCLRR_VREFEN RCC_MP_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MP_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MP_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3ENCLRR_DTSEN RCC_MP_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MP_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MP_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MP_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB3ENCLRR_HDPEN RCC_MP_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENSETR register ***************/ +#define RCC_MP_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENSETR_DMA1EN RCC_MP_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENSETR_DMA2EN RCC_MP_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENSETR_DMAMUXEN RCC_MP_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENSETR_ADC12EN RCC_MP_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENSETR_USBOEN RCC_MP_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENSETR_SDMMC3EN RCC_MP_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB2ENCLRR register ***************/ +#define RCC_MP_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MP_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2ENCLRR_DMA1EN RCC_MP_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MP_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2ENCLRR_DMA2EN RCC_MP_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2ENCLRR_DMAMUXEN RCC_MP_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MP_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2ENCLRR_ADC12EN RCC_MP_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MP_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MP_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2ENCLRR_USBOEN RCC_MP_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MP_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2ENCLRR_SDMMC3EN RCC_MP_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENSETR register ***************/ +#define RCC_MP_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENSETR_DCMIEN RCC_MP_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENSETR_CRYP2EN RCC_MP_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENSETR_HASH2EN RCC_MP_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENSETR_RNG2EN RCC_MP_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENSETR_CRC2EN RCC_MP_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENSETR_HSEMEN RCC_MP_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENSETR_IPCCEN RCC_MP_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB3ENCLRR register ***************/ +#define RCC_MP_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MP_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3ENCLRR_DCMIEN RCC_MP_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MP_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3ENCLRR_CRYP2EN RCC_MP_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MP_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3ENCLRR_HASH2EN RCC_MP_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MP_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3ENCLRR_RNG2EN RCC_MP_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MP_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MP_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3ENCLRR_CRC2EN RCC_MP_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MP_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3ENCLRR_HSEMEN RCC_MP_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MP_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MP_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MP_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3ENCLRR_IPCCEN RCC_MP_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENSETR register ***************/ +#define RCC_MP_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENSETR_GPIOAEN RCC_MP_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENSETR_GPIOBEN RCC_MP_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENSETR_GPIOCEN RCC_MP_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENSETR_GPIODEN RCC_MP_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENSETR_GPIOEEN RCC_MP_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENSETR_GPIOFEN RCC_MP_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENSETR_GPIOGEN RCC_MP_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENSETR_GPIOHEN RCC_MP_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENSETR_GPIOIEN RCC_MP_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENSETR_GPIOJEN RCC_MP_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENSETR_GPIOKEN RCC_MP_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_AHB4ENCLRR register ***************/ +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MP_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN RCC_MP_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MP_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4ENCLRR_GPIOBEN RCC_MP_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MP_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4ENCLRR_GPIOCEN RCC_MP_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MP_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4ENCLRR_GPIODEN RCC_MP_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MP_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4ENCLRR_GPIOEEN RCC_MP_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MP_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4ENCLRR_GPIOFEN RCC_MP_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MP_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4ENCLRR_GPIOGEN RCC_MP_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MP_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4ENCLRR_GPIOHEN RCC_MP_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MP_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4ENCLRR_GPIOIEN RCC_MP_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MP_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4ENCLRR_GPIOJEN RCC_MP_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MP_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MP_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4ENCLRR_GPIOKEN RCC_MP_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENSETR register **************/ +#define RCC_MP_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENSETR_RETRAMEN RCC_MP_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MP_MLAHBENCLRR register **************/ +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MP_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MP_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN RCC_MP_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENSETR register ***************/ +#define RCC_MC_APB1ENSETR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENSETR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENSETR_TIM2EN RCC_MC_APB1ENSETR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENSETR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENSETR_TIM3EN RCC_MC_APB1ENSETR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENSETR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENSETR_TIM4EN RCC_MC_APB1ENSETR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENSETR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENSETR_TIM5EN RCC_MC_APB1ENSETR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENSETR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENSETR_TIM6EN RCC_MC_APB1ENSETR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENSETR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENSETR_TIM7EN RCC_MC_APB1ENSETR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENSETR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENSETR_TIM12EN RCC_MC_APB1ENSETR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENSETR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENSETR_TIM13EN RCC_MC_APB1ENSETR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENSETR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENSETR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENSETR_TIM14EN RCC_MC_APB1ENSETR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENSETR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENSETR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENSETR_LPTIM1EN RCC_MC_APB1ENSETR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENSETR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENSETR_SPI2EN RCC_MC_APB1ENSETR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENSETR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENSETR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENSETR_SPI3EN RCC_MC_APB1ENSETR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENSETR_USART2EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENSETR_USART2EN RCC_MC_APB1ENSETR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENSETR_USART3EN_Msk (0x1U << RCC_MC_APB1ENSETR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENSETR_USART3EN RCC_MC_APB1ENSETR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENSETR_UART4EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENSETR_UART4EN RCC_MC_APB1ENSETR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENSETR_UART5EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENSETR_UART5EN RCC_MC_APB1ENSETR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENSETR_UART7EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENSETR_UART7EN RCC_MC_APB1ENSETR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENSETR_UART8EN_Msk (0x1U << RCC_MC_APB1ENSETR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENSETR_UART8EN RCC_MC_APB1ENSETR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENSETR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENSETR_I2C1EN RCC_MC_APB1ENSETR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENSETR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENSETR_I2C2EN RCC_MC_APB1ENSETR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENSETR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENSETR_I2C3EN RCC_MC_APB1ENSETR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENSETR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENSETR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENSETR_I2C5EN RCC_MC_APB1ENSETR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENSETR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENSETR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENSETR_SPDIFEN RCC_MC_APB1ENSETR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_CECEN_Pos (27U) +#define RCC_MC_APB1ENSETR_CECEN_Msk (0x1U << RCC_MC_APB1ENSETR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENSETR_CECEN RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_WWDG1EN_Pos (28U) +#define RCC_MC_APB1ENSETR_WWDG1EN_Msk (0x1U << RCC_MC_APB1ENSETR_WWDG1EN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1ENSETR_WWDG1EN RCC_MC_APB1ENSETR_WWDG1EN_Msk /*!< WWDG1 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENSETR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENSETR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENSETR_DAC12EN RCC_MC_APB1ENSETR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENSETR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENSETR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENSETR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENSETR_MDIOSEN RCC_MC_APB1ENSETR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB1ENCLRR register ***************/ +#define RCC_MC_APB1ENCLRR_TIM2EN_Pos (0U) +#define RCC_MC_APB1ENCLRR_TIM2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1ENCLRR_TIM2EN RCC_MC_APB1ENCLRR_TIM2EN_Msk /*!< TIM2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM3EN_Pos (1U) +#define RCC_MC_APB1ENCLRR_TIM3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1ENCLRR_TIM3EN RCC_MC_APB1ENCLRR_TIM3EN_Msk /*!< TIM3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM4EN_Pos (2U) +#define RCC_MC_APB1ENCLRR_TIM4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1ENCLRR_TIM4EN RCC_MC_APB1ENCLRR_TIM4EN_Msk /*!< TIM4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM5EN_Pos (3U) +#define RCC_MC_APB1ENCLRR_TIM5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1ENCLRR_TIM5EN RCC_MC_APB1ENCLRR_TIM5EN_Msk /*!< TIM5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM6EN_Pos (4U) +#define RCC_MC_APB1ENCLRR_TIM6EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1ENCLRR_TIM6EN RCC_MC_APB1ENCLRR_TIM6EN_Msk /*!< TIM6 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM7EN_Pos (5U) +#define RCC_MC_APB1ENCLRR_TIM7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1ENCLRR_TIM7EN RCC_MC_APB1ENCLRR_TIM7EN_Msk /*!< TIM7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM12EN_Pos (6U) +#define RCC_MC_APB1ENCLRR_TIM12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1ENCLRR_TIM12EN RCC_MC_APB1ENCLRR_TIM12EN_Msk /*!< TIM12 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM13EN_Pos (7U) +#define RCC_MC_APB1ENCLRR_TIM13EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1ENCLRR_TIM13EN RCC_MC_APB1ENCLRR_TIM13EN_Msk /*!< TIM13 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_TIM14EN_Pos (8U) +#define RCC_MC_APB1ENCLRR_TIM14EN_Msk (0x1U << RCC_MC_APB1ENCLRR_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1ENCLRR_TIM14EN RCC_MC_APB1ENCLRR_TIM14EN_Msk /*!< TIM14 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Pos (9U) +#define RCC_MC_APB1ENCLRR_LPTIM1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1ENCLRR_LPTIM1EN RCC_MC_APB1ENCLRR_LPTIM1EN_Msk /*!< LPTIM1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI2EN_Pos (11U) +#define RCC_MC_APB1ENCLRR_SPI2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI2EN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1ENCLRR_SPI2EN RCC_MC_APB1ENCLRR_SPI2EN_Msk /*!< SPI2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPI3EN_Pos (12U) +#define RCC_MC_APB1ENCLRR_SPI3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPI3EN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1ENCLRR_SPI3EN RCC_MC_APB1ENCLRR_SPI3EN_Msk /*!< SPI3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART2EN_Pos (14U) +#define RCC_MC_APB1ENCLRR_USART2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART2EN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1ENCLRR_USART2EN RCC_MC_APB1ENCLRR_USART2EN_Msk /*!< USART2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_USART3EN_Pos (15U) +#define RCC_MC_APB1ENCLRR_USART3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_USART3EN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1ENCLRR_USART3EN RCC_MC_APB1ENCLRR_USART3EN_Msk /*!< USART3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART4EN_Pos (16U) +#define RCC_MC_APB1ENCLRR_UART4EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART4EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1ENCLRR_UART4EN RCC_MC_APB1ENCLRR_UART4EN_Msk /*!< UART4 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART5EN_Pos (17U) +#define RCC_MC_APB1ENCLRR_UART5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART5EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1ENCLRR_UART5EN RCC_MC_APB1ENCLRR_UART5EN_Msk /*!< UART5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART7EN_Pos (18U) +#define RCC_MC_APB1ENCLRR_UART7EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART7EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1ENCLRR_UART7EN RCC_MC_APB1ENCLRR_UART7EN_Msk /*!< UART7 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_UART8EN_Pos (19U) +#define RCC_MC_APB1ENCLRR_UART8EN_Msk (0x1U << RCC_MC_APB1ENCLRR_UART8EN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1ENCLRR_UART8EN RCC_MC_APB1ENCLRR_UART8EN_Msk /*!< UART8 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C1EN_Pos (21U) +#define RCC_MC_APB1ENCLRR_I2C1EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1ENCLRR_I2C1EN RCC_MC_APB1ENCLRR_I2C1EN_Msk /*!< I2C1 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C2EN_Pos (22U) +#define RCC_MC_APB1ENCLRR_I2C2EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1ENCLRR_I2C2EN RCC_MC_APB1ENCLRR_I2C2EN_Msk /*!< I2C2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C3EN_Pos (23U) +#define RCC_MC_APB1ENCLRR_I2C3EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1ENCLRR_I2C3EN RCC_MC_APB1ENCLRR_I2C3EN_Msk /*!< I2C3 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_I2C5EN_Pos (24U) +#define RCC_MC_APB1ENCLRR_I2C5EN_Msk (0x1U << RCC_MC_APB1ENCLRR_I2C5EN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1ENCLRR_I2C5EN RCC_MC_APB1ENCLRR_I2C5EN_Msk /*!< I2C5 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_SPDIFEN_Pos (26U) +#define RCC_MC_APB1ENCLRR_SPDIFEN_Msk (0x1U << RCC_MC_APB1ENCLRR_SPDIFEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1ENCLRR_SPDIFEN RCC_MC_APB1ENCLRR_SPDIFEN_Msk /*!< SPDIFRX peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_CECEN_Pos (27U) +#define RCC_MC_APB1ENCLRR_CECEN_Msk (0x1U << RCC_MC_APB1ENCLRR_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1ENCLRR_CECEN RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_DAC12EN_Pos (29U) +#define RCC_MC_APB1ENCLRR_DAC12EN_Msk (0x1U << RCC_MC_APB1ENCLRR_DAC12EN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1ENCLRR_DAC12EN RCC_MC_APB1ENCLRR_DAC12EN_Msk /*!< DAC1&2 peripheral clocks enable */ +#define RCC_MC_APB1ENCLRR_MDIOSEN_Pos (31U) +#define RCC_MC_APB1ENCLRR_MDIOSEN_Msk (0x1U << RCC_MC_APB1ENCLRR_MDIOSEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1ENCLRR_MDIOSEN RCC_MC_APB1ENCLRR_MDIOSEN_Msk /*!< MDIOS peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENSETR register ***************/ +#define RCC_MC_APB2ENSETR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENSETR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENSETR_TIM1EN RCC_MC_APB2ENSETR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENSETR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENSETR_TIM8EN RCC_MC_APB2ENSETR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENSETR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENSETR_TIM15EN RCC_MC_APB2ENSETR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENSETR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENSETR_TIM16EN RCC_MC_APB2ENSETR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENSETR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENSETR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENSETR_TIM17EN RCC_MC_APB2ENSETR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENSETR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENSETR_SPI1EN RCC_MC_APB2ENSETR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENSETR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENSETR_SPI4EN RCC_MC_APB2ENSETR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENSETR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENSETR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENSETR_SPI5EN RCC_MC_APB2ENSETR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENSETR_USART6EN_Msk (0x1U << RCC_MC_APB2ENSETR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENSETR_USART6EN RCC_MC_APB2ENSETR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENSETR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENSETR_SAI1EN RCC_MC_APB2ENSETR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENSETR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENSETR_SAI2EN RCC_MC_APB2ENSETR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENSETR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENSETR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENSETR_SAI3EN RCC_MC_APB2ENSETR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENSETR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENSETR_DFSDMEN RCC_MC_APB2ENSETR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENSETR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENSETR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENSETR_ADFSDMEN RCC_MC_APB2ENSETR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENSETR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENSETR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENSETR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENSETR_FDCANEN RCC_MC_APB2ENSETR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB2ENCLRR register ***************/ +#define RCC_MC_APB2ENCLRR_TIM1EN_Pos (0U) +#define RCC_MC_APB2ENCLRR_TIM1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2ENCLRR_TIM1EN RCC_MC_APB2ENCLRR_TIM1EN_Msk /*!< TIM1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM8EN_Pos (1U) +#define RCC_MC_APB2ENCLRR_TIM8EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM8EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2ENCLRR_TIM8EN RCC_MC_APB2ENCLRR_TIM8EN_Msk /*!< TIM8 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM15EN_Pos (2U) +#define RCC_MC_APB2ENCLRR_TIM15EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM15EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2ENCLRR_TIM15EN RCC_MC_APB2ENCLRR_TIM15EN_Msk /*!< TIM15 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM16EN_Pos (3U) +#define RCC_MC_APB2ENCLRR_TIM16EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM16EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2ENCLRR_TIM16EN RCC_MC_APB2ENCLRR_TIM16EN_Msk /*!< TIM16 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_TIM17EN_Pos (4U) +#define RCC_MC_APB2ENCLRR_TIM17EN_Msk (0x1U << RCC_MC_APB2ENCLRR_TIM17EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2ENCLRR_TIM17EN RCC_MC_APB2ENCLRR_TIM17EN_Msk /*!< TIM17 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI1EN_Pos (8U) +#define RCC_MC_APB2ENCLRR_SPI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI1EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2ENCLRR_SPI1EN RCC_MC_APB2ENCLRR_SPI1EN_Msk /*!< SPI/I2S1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI4EN_Pos (9U) +#define RCC_MC_APB2ENCLRR_SPI4EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI4EN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2ENCLRR_SPI4EN RCC_MC_APB2ENCLRR_SPI4EN_Msk /*!< SPI4 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SPI5EN_Pos (10U) +#define RCC_MC_APB2ENCLRR_SPI5EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SPI5EN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2ENCLRR_SPI5EN RCC_MC_APB2ENCLRR_SPI5EN_Msk /*!< SPI5 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_USART6EN_Pos (13U) +#define RCC_MC_APB2ENCLRR_USART6EN_Msk (0x1U << RCC_MC_APB2ENCLRR_USART6EN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2ENCLRR_USART6EN RCC_MC_APB2ENCLRR_USART6EN_Msk /*!< USART6 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI1EN_Pos (16U) +#define RCC_MC_APB2ENCLRR_SAI1EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI1EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2ENCLRR_SAI1EN RCC_MC_APB2ENCLRR_SAI1EN_Msk /*!< SAI1 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI2EN_Pos (17U) +#define RCC_MC_APB2ENCLRR_SAI2EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI2EN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2ENCLRR_SAI2EN RCC_MC_APB2ENCLRR_SAI2EN_Msk /*!< SAI2 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_SAI3EN_Pos (18U) +#define RCC_MC_APB2ENCLRR_SAI3EN_Msk (0x1U << RCC_MC_APB2ENCLRR_SAI3EN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2ENCLRR_SAI3EN RCC_MC_APB2ENCLRR_SAI3EN_Msk /*!< SAI3 peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_DFSDMEN_Pos (20U) +#define RCC_MC_APB2ENCLRR_DFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_DFSDMEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2ENCLRR_DFSDMEN RCC_MC_APB2ENCLRR_DFSDMEN_Msk /*!< DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Pos (21U) +#define RCC_MC_APB2ENCLRR_ADFSDMEN_Msk (0x1U << RCC_MC_APB2ENCLRR_ADFSDMEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2ENCLRR_ADFSDMEN RCC_MC_APB2ENCLRR_ADFSDMEN_Msk /*!< Audio DFSDM peripheral clocks enable */ +#define RCC_MC_APB2ENCLRR_FDCANEN_Pos (24U) +#define RCC_MC_APB2ENCLRR_FDCANEN_Msk (0x1U << RCC_MC_APB2ENCLRR_FDCANEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2ENCLRR_FDCANEN RCC_MC_APB2ENCLRR_FDCANEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENSETR register ***************/ +#define RCC_MC_APB3ENSETR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENSETR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENSETR_LPTIM2EN RCC_MC_APB3ENSETR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENSETR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENSETR_LPTIM3EN RCC_MC_APB3ENSETR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENSETR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENSETR_LPTIM4EN RCC_MC_APB3ENSETR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENSETR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENSETR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENSETR_LPTIM5EN RCC_MC_APB3ENSETR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENSETR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENSETR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENSETR_SAI4EN RCC_MC_APB3ENSETR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENSETR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENSETR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENSETR_SYSCFGEN RCC_MC_APB3ENSETR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENSETR_VREFEN_Msk (0x1U << RCC_MC_APB3ENSETR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENSETR_VREFEN RCC_MC_APB3ENSETR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENSETR_DTSEN_Msk (0x1U << RCC_MC_APB3ENSETR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENSETR_DTSEN RCC_MC_APB3ENSETR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENSETR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENSETR_HDPEN_Msk (0x1U << RCC_MC_APB3ENSETR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENSETR_HDPEN RCC_MC_APB3ENSETR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_APB3ENCLRR register ***************/ +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Pos (0U) +#define RCC_MC_APB3ENCLRR_LPTIM2EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN RCC_MC_APB3ENCLRR_LPTIM2EN_Msk /*!< LPTIM2 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Pos (1U) +#define RCC_MC_APB3ENCLRR_LPTIM3EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3ENCLRR_LPTIM3EN RCC_MC_APB3ENCLRR_LPTIM3EN_Msk /*!< LPTIM3 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Pos (2U) +#define RCC_MC_APB3ENCLRR_LPTIM4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3ENCLRR_LPTIM4EN RCC_MC_APB3ENCLRR_LPTIM4EN_Msk /*!< LPTIM4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Pos (3U) +#define RCC_MC_APB3ENCLRR_LPTIM5EN_Msk (0x1U << RCC_MC_APB3ENCLRR_LPTIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3ENCLRR_LPTIM5EN RCC_MC_APB3ENCLRR_LPTIM5EN_Msk /*!< LPTIM5 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SAI4EN_Pos (8U) +#define RCC_MC_APB3ENCLRR_SAI4EN_Msk (0x1U << RCC_MC_APB3ENCLRR_SAI4EN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3ENCLRR_SAI4EN RCC_MC_APB3ENCLRR_SAI4EN_Msk /*!< SAI4 peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Pos (11U) +#define RCC_MC_APB3ENCLRR_SYSCFGEN_Msk (0x1U << RCC_MC_APB3ENCLRR_SYSCFGEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3ENCLRR_SYSCFGEN RCC_MC_APB3ENCLRR_SYSCFGEN_Msk /*!< SYSCFG peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_VREFEN_Pos (13U) +#define RCC_MC_APB3ENCLRR_VREFEN_Msk (0x1U << RCC_MC_APB3ENCLRR_VREFEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3ENCLRR_VREFEN RCC_MC_APB3ENCLRR_VREFEN_Msk /*!< VREF peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_DTSEN_Pos (16U) +#define RCC_MC_APB3ENCLRR_DTSEN_Msk (0x1U << RCC_MC_APB3ENCLRR_DTSEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3ENCLRR_DTSEN RCC_MC_APB3ENCLRR_DTSEN_Msk /*!< DTS peripheral clocks enable */ +#define RCC_MC_APB3ENCLRR_HDPEN_Pos (20U) +#define RCC_MC_APB3ENCLRR_HDPEN_Msk (0x1U << RCC_MC_APB3ENCLRR_HDPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB3ENCLRR_HDPEN RCC_MC_APB3ENCLRR_HDPEN_Msk /*!< HDP peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENSETR register ***************/ +#define RCC_MC_AHB2ENSETR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENSETR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENSETR_DMA1EN RCC_MC_AHB2ENSETR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENSETR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENSETR_DMA2EN RCC_MC_AHB2ENSETR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENSETR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENSETR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENSETR_DMAMUXEN RCC_MC_AHB2ENSETR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENSETR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENSETR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENSETR_ADC12EN RCC_MC_AHB2ENSETR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENSETR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENSETR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENSETR_USBOEN RCC_MC_AHB2ENSETR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENSETR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENSETR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENSETR_SDMMC3EN RCC_MC_AHB2ENSETR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB2ENCLRR register ***************/ +#define RCC_MC_AHB2ENCLRR_DMA1EN_Pos (0U) +#define RCC_MC_AHB2ENCLRR_DMA1EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2ENCLRR_DMA1EN RCC_MC_AHB2ENCLRR_DMA1EN_Msk /*!< DMA1 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMA2EN_Pos (1U) +#define RCC_MC_AHB2ENCLRR_DMA2EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMA2EN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2ENCLRR_DMA2EN RCC_MC_AHB2ENCLRR_DMA2EN_Msk /*!< DMA2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos (2U) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_DMAMUXEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2ENCLRR_DMAMUXEN RCC_MC_AHB2ENCLRR_DMAMUXEN_Msk /*!< DMAMUX peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_ADC12EN_Pos (5U) +#define RCC_MC_AHB2ENCLRR_ADC12EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2ENCLRR_ADC12EN RCC_MC_AHB2ENCLRR_ADC12EN_Msk /*!< ADC1&2 peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_USBOEN_Pos (8U) +#define RCC_MC_AHB2ENCLRR_USBOEN_Msk (0x1U << RCC_MC_AHB2ENCLRR_USBOEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2ENCLRR_USBOEN RCC_MC_AHB2ENCLRR_USBOEN_Msk /*!< USBO peripheral clocks enable */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos (16U) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk (0x1U << RCC_MC_AHB2ENCLRR_SDMMC3EN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2ENCLRR_SDMMC3EN RCC_MC_AHB2ENCLRR_SDMMC3EN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENSETR register ***************/ +#define RCC_MC_AHB3ENSETR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENSETR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENSETR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENSETR_DCMIEN RCC_MC_AHB3ENSETR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENSETR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENSETR_CRYP2EN RCC_MC_AHB3ENSETR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENSETR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENSETR_HASH2EN RCC_MC_AHB3ENSETR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENSETR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENSETR_RNG2EN RCC_MC_AHB3ENSETR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENSETR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENSETR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENSETR_CRC2EN RCC_MC_AHB3ENSETR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENSETR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENSETR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENSETR_HSEMEN RCC_MC_AHB3ENSETR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENSETR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENSETR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENSETR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENSETR_IPCCEN RCC_MC_AHB3ENSETR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB3ENCLRR register ***************/ +#define RCC_MC_AHB3ENCLRR_DCMIEN_Pos (0U) +#define RCC_MC_AHB3ENCLRR_DCMIEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_DCMIEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3ENCLRR_DCMIEN RCC_MC_AHB3ENCLRR_DCMIEN_Msk /*!< DCMI peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Pos (4U) +#define RCC_MC_AHB3ENCLRR_CRYP2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRYP2EN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3ENCLRR_CRYP2EN RCC_MC_AHB3ENCLRR_CRYP2EN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HASH2EN_Pos (5U) +#define RCC_MC_AHB3ENCLRR_HASH2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HASH2EN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3ENCLRR_HASH2EN RCC_MC_AHB3ENCLRR_HASH2EN_Msk /*!< HASH2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_RNG2EN_Pos (6U) +#define RCC_MC_AHB3ENCLRR_RNG2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_RNG2EN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3ENCLRR_RNG2EN RCC_MC_AHB3ENCLRR_RNG2EN_Msk /*!< RNG2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_CRC2EN_Pos (7U) +#define RCC_MC_AHB3ENCLRR_CRC2EN_Msk (0x1U << RCC_MC_AHB3ENCLRR_CRC2EN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3ENCLRR_CRC2EN RCC_MC_AHB3ENCLRR_CRC2EN_Msk /*!< CRC2 peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_HSEMEN_Pos (11U) +#define RCC_MC_AHB3ENCLRR_HSEMEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_HSEMEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3ENCLRR_HSEMEN RCC_MC_AHB3ENCLRR_HSEMEN_Msk /*!< HSEM peripheral clocks enable */ +#define RCC_MC_AHB3ENCLRR_IPCCEN_Pos (12U) +#define RCC_MC_AHB3ENCLRR_IPCCEN_Msk (0x1U << RCC_MC_AHB3ENCLRR_IPCCEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3ENCLRR_IPCCEN RCC_MC_AHB3ENCLRR_IPCCEN_Msk /*!< IPCC peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENSETR register ***************/ +#define RCC_MC_AHB4ENSETR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENSETR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENSETR_GPIOAEN RCC_MC_AHB4ENSETR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENSETR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENSETR_GPIOBEN RCC_MC_AHB4ENSETR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENSETR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENSETR_GPIOCEN RCC_MC_AHB4ENSETR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENSETR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENSETR_GPIODEN RCC_MC_AHB4ENSETR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENSETR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENSETR_GPIOEEN RCC_MC_AHB4ENSETR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENSETR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENSETR_GPIOFEN RCC_MC_AHB4ENSETR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENSETR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENSETR_GPIOGEN RCC_MC_AHB4ENSETR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENSETR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENSETR_GPIOHEN RCC_MC_AHB4ENSETR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENSETR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENSETR_GPIOIEN RCC_MC_AHB4ENSETR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENSETR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENSETR_GPIOJEN RCC_MC_AHB4ENSETR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENSETR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENSETR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENSETR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENSETR_GPIOKEN RCC_MC_AHB4ENSETR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AHB4ENCLRR register ***************/ +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Pos (0U) +#define RCC_MC_AHB4ENCLRR_GPIOAEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN RCC_MC_AHB4ENCLRR_GPIOAEN_Msk /*!< GPIOA peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Pos (1U) +#define RCC_MC_AHB4ENCLRR_GPIOBEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4ENCLRR_GPIOBEN RCC_MC_AHB4ENCLRR_GPIOBEN_Msk /*!< GPIOB peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Pos (2U) +#define RCC_MC_AHB4ENCLRR_GPIOCEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4ENCLRR_GPIOCEN RCC_MC_AHB4ENCLRR_GPIOCEN_Msk /*!< GPIOC peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIODEN_Pos (3U) +#define RCC_MC_AHB4ENCLRR_GPIODEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4ENCLRR_GPIODEN RCC_MC_AHB4ENCLRR_GPIODEN_Msk /*!< GPIOD peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Pos (4U) +#define RCC_MC_AHB4ENCLRR_GPIOEEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4ENCLRR_GPIOEEN RCC_MC_AHB4ENCLRR_GPIOEEN_Msk /*!< GPIOE peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Pos (5U) +#define RCC_MC_AHB4ENCLRR_GPIOFEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4ENCLRR_GPIOFEN RCC_MC_AHB4ENCLRR_GPIOFEN_Msk /*!< GPIOF peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Pos (6U) +#define RCC_MC_AHB4ENCLRR_GPIOGEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4ENCLRR_GPIOGEN RCC_MC_AHB4ENCLRR_GPIOGEN_Msk /*!< GPIOG peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Pos (7U) +#define RCC_MC_AHB4ENCLRR_GPIOHEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4ENCLRR_GPIOHEN RCC_MC_AHB4ENCLRR_GPIOHEN_Msk /*!< GPIOH peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Pos (8U) +#define RCC_MC_AHB4ENCLRR_GPIOIEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOIEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4ENCLRR_GPIOIEN RCC_MC_AHB4ENCLRR_GPIOIEN_Msk /*!< GPIOI peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Pos (9U) +#define RCC_MC_AHB4ENCLRR_GPIOJEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOJEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4ENCLRR_GPIOJEN RCC_MC_AHB4ENCLRR_GPIOJEN_Msk /*!< GPIOJ peripheral clocks enable */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Pos (10U) +#define RCC_MC_AHB4ENCLRR_GPIOKEN_Msk (0x1U << RCC_MC_AHB4ENCLRR_GPIOKEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4ENCLRR_GPIOKEN RCC_MC_AHB4ENCLRR_GPIOKEN_Msk /*!< GPIOK peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENSETR register ***************/ +#define RCC_MC_AXIMENSETR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENSETR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENSETR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENSETR_SYSRAMEN RCC_MC_AXIMENSETR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_AXIMENCLRR register ***************/ +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Pos (0U) +#define RCC_MC_AXIMENCLRR_SYSRAMEN_Msk (0x1U << RCC_MC_AXIMENCLRR_SYSRAMEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN RCC_MC_AXIMENCLRR_SYSRAMEN_Msk /*!< SYSRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENSETR register **************/ +#define RCC_MC_MLAHBENSETR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENSETR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENSETR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENSETR_RETRAMEN RCC_MC_MLAHBENSETR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************** Bit definition for RCC_MC_MLAHBENCLRR register **************/ +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Pos (4U) +#define RCC_MC_MLAHBENCLRR_RETRAMEN_Msk (0x1U << RCC_MC_MLAHBENCLRR_RETRAMEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN RCC_MC_MLAHBENCLRR_RETRAMEN_Msk /*!< RETRAM peripheral clocks enable */ + +/************* Bit definition for RCC_MP_APB1LPENSETR register **************/ +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN RCC_MP_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENSETR_TIM3LPEN RCC_MP_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENSETR_TIM4LPEN RCC_MP_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENSETR_TIM5LPEN RCC_MP_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENSETR_TIM6LPEN RCC_MP_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENSETR_TIM7LPEN RCC_MP_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENSETR_TIM12LPEN RCC_MP_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENSETR_TIM13LPEN RCC_MP_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENSETR_TIM14LPEN RCC_MP_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN RCC_MP_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENSETR_SPI2LPEN RCC_MP_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENSETR_SPI3LPEN RCC_MP_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENSETR_USART2LPEN RCC_MP_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENSETR_USART3LPEN RCC_MP_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENSETR_UART4LPEN RCC_MP_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENSETR_UART5LPEN RCC_MP_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENSETR_UART7LPEN RCC_MP_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENSETR_UART8LPEN RCC_MP_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENSETR_I2C1LPEN RCC_MP_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENSETR_I2C2LPEN RCC_MP_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENSETR_I2C3LPEN RCC_MP_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENSETR_I2C5LPEN RCC_MP_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENSETR_SPDIFLPEN RCC_MP_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENSETR_CECLPEN RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENSETR_DAC12LPEN RCC_MP_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENSETR_MDIOSLPEN RCC_MP_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB1LPENCLRR register **************/ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN RCC_MP_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB1LPENCLRR_TIM3LPEN RCC_MP_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB1LPENCLRR_TIM4LPEN RCC_MP_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB1LPENCLRR_TIM5LPEN RCC_MP_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB1LPENCLRR_TIM6LPEN RCC_MP_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_APB1LPENCLRR_TIM7LPEN RCC_MP_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_APB1LPENCLRR_TIM12LPEN RCC_MP_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_APB1LPENCLRR_TIM13LPEN RCC_MP_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB1LPENCLRR_TIM14LPEN RCC_MP_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN RCC_MP_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB1LPENCLRR_SPI2LPEN RCC_MP_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_APB1LPENCLRR_SPI3LPEN RCC_MP_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MP_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MP_APB1LPENCLRR_USART2LPEN RCC_MP_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MP_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MP_APB1LPENCLRR_USART3LPEN RCC_MP_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MP_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB1LPENCLRR_UART4LPEN RCC_MP_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MP_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB1LPENCLRR_UART5LPEN RCC_MP_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MP_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB1LPENCLRR_UART7LPEN RCC_MP_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MP_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MP_APB1LPENCLRR_UART8LPEN RCC_MP_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB1LPENCLRR_I2C1LPEN RCC_MP_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MP_APB1LPENCLRR_I2C2LPEN RCC_MP_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MP_APB1LPENCLRR_I2C3LPEN RCC_MP_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB1LPENCLRR_I2C5LPEN RCC_MP_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN RCC_MP_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MP_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MP_APB1LPENCLRR_CECLPEN RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MP_APB1LPENCLRR_DAC12LPEN RCC_MP_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MP_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN RCC_MP_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENSETR register **************/ +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN RCC_MP_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENSETR_TIM8LPEN RCC_MP_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENSETR_TIM15LPEN RCC_MP_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENSETR_TIM16LPEN RCC_MP_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENSETR_TIM17LPEN RCC_MP_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENSETR_SPI1LPEN RCC_MP_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENSETR_SPI4LPEN RCC_MP_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENSETR_SPI5LPEN RCC_MP_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENSETR_USART6LPEN RCC_MP_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENSETR_SAI1LPEN RCC_MP_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENSETR_SAI2LPEN RCC_MP_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENSETR_SAI3LPEN RCC_MP_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENSETR_DFSDMLPEN RCC_MP_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN RCC_MP_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENSETR_FDCANLPEN RCC_MP_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB2LPENCLRR register **************/ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN RCC_MP_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB2LPENCLRR_TIM8LPEN RCC_MP_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB2LPENCLRR_TIM15LPEN RCC_MP_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB2LPENCLRR_TIM16LPEN RCC_MP_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_APB2LPENCLRR_TIM17LPEN RCC_MP_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB2LPENCLRR_SPI1LPEN RCC_MP_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_APB2LPENCLRR_SPI4LPEN RCC_MP_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_APB2LPENCLRR_SPI5LPEN RCC_MP_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MP_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB2LPENCLRR_USART6LPEN RCC_MP_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB2LPENCLRR_SAI1LPEN RCC_MP_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MP_APB2LPENCLRR_SAI2LPEN RCC_MP_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MP_APB2LPENCLRR_SAI3LPEN RCC_MP_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN RCC_MP_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN RCC_MP_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MP_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MP_APB2LPENCLRR_FDCANLPEN RCC_MP_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENSETR register **************/ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN RCC_MP_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN RCC_MP_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN RCC_MP_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN RCC_MP_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENSETR_SAI4LPEN RCC_MP_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN RCC_MP_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENSETR_VREFLPEN RCC_MP_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENSETR_DTSLPEN RCC_MP_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_APB3LPENCLRR register **************/ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN RCC_MP_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN RCC_MP_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN RCC_MP_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN RCC_MP_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_APB3LPENCLRR_SAI4LPEN RCC_MP_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN RCC_MP_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MP_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MP_APB3LPENCLRR_VREFLPEN RCC_MP_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MP_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MP_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_APB3LPENCLRR_DTSLPEN RCC_MP_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENSETR register **************/ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN RCC_MP_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENSETR_DMA2LPEN RCC_MP_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN RCC_MP_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENSETR_ADC12LPEN RCC_MP_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENSETR_USBOLPEN RCC_MP_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN RCC_MP_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB2LPENCLRR register **************/ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN RCC_MP_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN RCC_MP_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN RCC_MP_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN RCC_MP_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB2LPENCLRR_USBOLPEN RCC_MP_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN RCC_MP_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENSETR register **************/ +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN RCC_MP_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN RCC_MP_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENSETR_HASH2LPEN RCC_MP_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENSETR_RNG2LPEN RCC_MP_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENSETR_CRC2LPEN RCC_MP_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENSETR_HSEMLPEN RCC_MP_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENSETR_IPCCLPEN RCC_MP_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB3LPENCLRR register **************/ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN RCC_MP_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN RCC_MP_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN RCC_MP_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN RCC_MP_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN RCC_MP_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN RCC_MP_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MP_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN RCC_MP_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENSETR register **************/ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN RCC_MP_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN RCC_MP_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN RCC_MP_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENSETR_GPIODLPEN RCC_MP_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENSETR_GPIOELPEN RCC_MP_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN RCC_MP_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN RCC_MP_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN RCC_MP_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENSETR_GPIOILPEN RCC_MP_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN RCC_MP_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN RCC_MP_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AHB4LPENCLRR register **************/ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN RCC_MP_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN RCC_MP_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN RCC_MP_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN RCC_MP_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN RCC_MP_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN RCC_MP_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN RCC_MP_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN RCC_MP_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN RCC_MP_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN RCC_MP_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN RCC_MP_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENSETR register **************/ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN RCC_MP_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_AXIMLPENCLRR register **************/ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN RCC_MP_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENSETR register *************/ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN RCC_MP_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN RCC_MP_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN RCC_MP_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN RCC_MP_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MP_MLAHBLPENCLRR register *************/ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN RCC_MP_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN RCC_MP_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN RCC_MP_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN RCC_MP_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENSETR register **************/ +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENSETR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN RCC_MC_APB1LPENSETR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENSETR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENSETR_TIM3LPEN RCC_MC_APB1LPENSETR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENSETR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENSETR_TIM4LPEN RCC_MC_APB1LPENSETR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENSETR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENSETR_TIM5LPEN RCC_MC_APB1LPENSETR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENSETR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENSETR_TIM6LPEN RCC_MC_APB1LPENSETR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENSETR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENSETR_TIM7LPEN RCC_MC_APB1LPENSETR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENSETR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENSETR_TIM12LPEN RCC_MC_APB1LPENSETR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENSETR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENSETR_TIM13LPEN RCC_MC_APB1LPENSETR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENSETR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENSETR_TIM14LPEN RCC_MC_APB1LPENSETR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN RCC_MC_APB1LPENSETR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENSETR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENSETR_SPI2LPEN RCC_MC_APB1LPENSETR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENSETR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENSETR_SPI3LPEN RCC_MC_APB1LPENSETR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENSETR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENSETR_USART2LPEN RCC_MC_APB1LPENSETR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENSETR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENSETR_USART3LPEN RCC_MC_APB1LPENSETR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENSETR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENSETR_UART4LPEN RCC_MC_APB1LPENSETR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENSETR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENSETR_UART5LPEN RCC_MC_APB1LPENSETR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENSETR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENSETR_UART7LPEN RCC_MC_APB1LPENSETR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENSETR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENSETR_UART8LPEN RCC_MC_APB1LPENSETR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENSETR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENSETR_I2C1LPEN RCC_MC_APB1LPENSETR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENSETR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENSETR_I2C2LPEN RCC_MC_APB1LPENSETR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENSETR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENSETR_I2C3LPEN RCC_MC_APB1LPENSETR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENSETR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENSETR_I2C5LPEN RCC_MC_APB1LPENSETR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENSETR_SPDIFLPEN RCC_MC_APB1LPENSETR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENSETR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENSETR_CECLPEN RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENSETR_WWDG1LPEN RCC_MC_APB1LPENSETR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENSETR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENSETR_DAC12LPEN RCC_MC_APB1LPENSETR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENSETR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENSETR_MDIOSLPEN RCC_MC_APB1LPENSETR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB1LPENCLRR register **************/ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos (0U) +#define RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN RCC_MC_APB1LPENCLRR_TIM2LPEN_Msk /*!< TIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos (1U) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB1LPENCLRR_TIM3LPEN RCC_MC_APB1LPENCLRR_TIM3LPEN_Msk /*!< TIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos (2U) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB1LPENCLRR_TIM4LPEN RCC_MC_APB1LPENCLRR_TIM4LPEN_Msk /*!< TIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos (3U) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB1LPENCLRR_TIM5LPEN RCC_MC_APB1LPENCLRR_TIM5LPEN_Msk /*!< TIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos (4U) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB1LPENCLRR_TIM6LPEN RCC_MC_APB1LPENCLRR_TIM6LPEN_Msk /*!< TIM6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos (5U) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_APB1LPENCLRR_TIM7LPEN RCC_MC_APB1LPENCLRR_TIM7LPEN_Msk /*!< TIM7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos (6U) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_APB1LPENCLRR_TIM12LPEN RCC_MC_APB1LPENCLRR_TIM12LPEN_Msk /*!< TIM12 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos (7U) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_APB1LPENCLRR_TIM13LPEN RCC_MC_APB1LPENCLRR_TIM13LPEN_Msk /*!< TIM13 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos (8U) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB1LPENCLRR_TIM14LPEN RCC_MC_APB1LPENCLRR_TIM14LPEN_Msk /*!< TIM14 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos (9U) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN RCC_MC_APB1LPENCLRR_LPTIM1LPEN_Msk /*!< LPTIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos (11U) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI2LPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB1LPENCLRR_SPI2LPEN RCC_MC_APB1LPENCLRR_SPI2LPEN_Msk /*!< SPI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos (12U) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPI3LPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_APB1LPENCLRR_SPI3LPEN RCC_MC_APB1LPENCLRR_SPI3LPEN_Msk /*!< SPI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Pos (14U) +#define RCC_MC_APB1LPENCLRR_USART2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_MC_APB1LPENCLRR_USART2LPEN RCC_MC_APB1LPENCLRR_USART2LPEN_Msk /*!< USART2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Pos (15U) +#define RCC_MC_APB1LPENCLRR_USART3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_USART3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_MC_APB1LPENCLRR_USART3LPEN RCC_MC_APB1LPENCLRR_USART3LPEN_Msk /*!< USART3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Pos (16U) +#define RCC_MC_APB1LPENCLRR_UART4LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART4LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB1LPENCLRR_UART4LPEN RCC_MC_APB1LPENCLRR_UART4LPEN_Msk /*!< UART4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Pos (17U) +#define RCC_MC_APB1LPENCLRR_UART5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART5LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB1LPENCLRR_UART5LPEN RCC_MC_APB1LPENCLRR_UART5LPEN_Msk /*!< UART5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Pos (18U) +#define RCC_MC_APB1LPENCLRR_UART7LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART7LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB1LPENCLRR_UART7LPEN RCC_MC_APB1LPENCLRR_UART7LPEN_Msk /*!< UART7 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Pos (19U) +#define RCC_MC_APB1LPENCLRR_UART8LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_UART8LPEN_Pos) /*!< 0x00080000 */ +#define RCC_MC_APB1LPENCLRR_UART8LPEN RCC_MC_APB1LPENCLRR_UART8LPEN_Msk /*!< UART8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos (21U) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB1LPENCLRR_I2C1LPEN RCC_MC_APB1LPENCLRR_I2C1LPEN_Msk /*!< I2C1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos (22U) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_MC_APB1LPENCLRR_I2C2LPEN RCC_MC_APB1LPENCLRR_I2C2LPEN_Msk /*!< I2C2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos (23U) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_MC_APB1LPENCLRR_I2C3LPEN RCC_MC_APB1LPENCLRR_I2C3LPEN_Msk /*!< I2C3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos (24U) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_I2C5LPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB1LPENCLRR_I2C5LPEN RCC_MC_APB1LPENCLRR_I2C5LPEN_Msk /*!< I2C5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos (26U) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_SPDIFLPEN_Pos) /*!< 0x04000000 */ +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN RCC_MC_APB1LPENCLRR_SPDIFLPEN_Msk /*!< SPDIFRX peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_CECLPEN_Pos (27U) +#define RCC_MC_APB1LPENCLRR_CECLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_MC_APB1LPENCLRR_CECLPEN RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos (28U) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_WWDG1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN RCC_MC_APB1LPENCLRR_WWDG1LPEN_Msk /*!< WWDG1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos (29U) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_DAC12LPEN_Pos) /*!< 0x20000000 */ +#define RCC_MC_APB1LPENCLRR_DAC12LPEN RCC_MC_APB1LPENCLRR_DAC12LPEN_Msk /*!< DAC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos (31U) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk (0x1U << RCC_MC_APB1LPENCLRR_MDIOSLPEN_Pos) /*!< 0x80000000 */ +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN RCC_MC_APB1LPENCLRR_MDIOSLPEN_Msk /*!< MDIOS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENSETR register **************/ +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENSETR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN RCC_MC_APB2LPENSETR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENSETR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENSETR_TIM8LPEN RCC_MC_APB2LPENSETR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENSETR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENSETR_TIM15LPEN RCC_MC_APB2LPENSETR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENSETR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENSETR_TIM16LPEN RCC_MC_APB2LPENSETR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENSETR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENSETR_TIM17LPEN RCC_MC_APB2LPENSETR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENSETR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENSETR_SPI1LPEN RCC_MC_APB2LPENSETR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENSETR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENSETR_SPI4LPEN RCC_MC_APB2LPENSETR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENSETR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENSETR_SPI5LPEN RCC_MC_APB2LPENSETR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENSETR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENSETR_USART6LPEN RCC_MC_APB2LPENSETR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENSETR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENSETR_SAI1LPEN RCC_MC_APB2LPENSETR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENSETR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENSETR_SAI2LPEN RCC_MC_APB2LPENSETR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENSETR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENSETR_SAI3LPEN RCC_MC_APB2LPENSETR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENSETR_DFSDMLPEN RCC_MC_APB2LPENSETR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN RCC_MC_APB2LPENSETR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENSETR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENSETR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENSETR_FDCANLPEN RCC_MC_APB2LPENSETR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB2LPENCLRR register **************/ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos (0U) +#define RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN RCC_MC_APB2LPENCLRR_TIM1LPEN_Msk /*!< TIM1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos (1U) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM8LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB2LPENCLRR_TIM8LPEN RCC_MC_APB2LPENCLRR_TIM8LPEN_Msk /*!< TIM8 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos (2U) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM15LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB2LPENCLRR_TIM15LPEN RCC_MC_APB2LPENCLRR_TIM15LPEN_Msk /*!< TIM15 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos (3U) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM16LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB2LPENCLRR_TIM16LPEN RCC_MC_APB2LPENCLRR_TIM16LPEN_Msk /*!< TIM16 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos (4U) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_TIM17LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_APB2LPENCLRR_TIM17LPEN RCC_MC_APB2LPENCLRR_TIM17LPEN_Msk /*!< TIM17 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos (8U) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB2LPENCLRR_SPI1LPEN RCC_MC_APB2LPENCLRR_SPI1LPEN_Msk /*!< SPI/I2S1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos (9U) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI4LPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_APB2LPENCLRR_SPI4LPEN RCC_MC_APB2LPENCLRR_SPI4LPEN_Msk /*!< SPI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos (10U) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SPI5LPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_APB2LPENCLRR_SPI5LPEN RCC_MC_APB2LPENCLRR_SPI5LPEN_Msk /*!< SPI5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Pos (13U) +#define RCC_MC_APB2LPENCLRR_USART6LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_USART6LPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB2LPENCLRR_USART6LPEN RCC_MC_APB2LPENCLRR_USART6LPEN_Msk /*!< USART6 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos (16U) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI1LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB2LPENCLRR_SAI1LPEN RCC_MC_APB2LPENCLRR_SAI1LPEN_Msk /*!< SAI1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos (17U) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI2LPEN_Pos) /*!< 0x00020000 */ +#define RCC_MC_APB2LPENCLRR_SAI2LPEN RCC_MC_APB2LPENCLRR_SAI2LPEN_Msk /*!< SAI2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos (18U) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_SAI3LPEN_Pos) /*!< 0x00040000 */ +#define RCC_MC_APB2LPENCLRR_SAI3LPEN RCC_MC_APB2LPENCLRR_SAI3LPEN_Msk /*!< SAI3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos (20U) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_DFSDMLPEN_Pos) /*!< 0x00100000 */ +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN RCC_MC_APB2LPENCLRR_DFSDMLPEN_Msk /*!< DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos (21U) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Pos) /*!< 0x00200000 */ +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN RCC_MC_APB2LPENCLRR_ADFSDMLPEN_Msk /*!< Audio DFSDM peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos (24U) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk (0x1U << RCC_MC_APB2LPENCLRR_FDCANLPEN_Pos) /*!< 0x01000000 */ +#define RCC_MC_APB2LPENCLRR_FDCANLPEN RCC_MC_APB2LPENCLRR_FDCANLPEN_Msk /*!< FDCAN and CANRAM peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENSETR register **************/ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN RCC_MC_APB3LPENSETR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN RCC_MC_APB3LPENSETR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN RCC_MC_APB3LPENSETR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN RCC_MC_APB3LPENSETR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENSETR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENSETR_SAI4LPEN RCC_MC_APB3LPENSETR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN RCC_MC_APB3LPENSETR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENSETR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENSETR_VREFLPEN RCC_MC_APB3LPENSETR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENSETR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENSETR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENSETR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENSETR_DTSLPEN RCC_MC_APB3LPENSETR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_APB3LPENCLRR register **************/ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos (0U) +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN RCC_MC_APB3LPENCLRR_LPTIM2LPEN_Msk /*!< LPTIM2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos (1U) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN RCC_MC_APB3LPENCLRR_LPTIM3LPEN_Msk /*!< LPTIM3 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos (2U) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN RCC_MC_APB3LPENCLRR_LPTIM4LPEN_Msk /*!< LPTIM4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos (3U) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN RCC_MC_APB3LPENCLRR_LPTIM5LPEN_Msk /*!< LPTIM5 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos (8U) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SAI4LPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_APB3LPENCLRR_SAI4LPEN RCC_MC_APB3LPENCLRR_SAI4LPEN_Msk /*!< SAI4 peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos (11U) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN RCC_MC_APB3LPENCLRR_SYSCFGLPEN_Msk /*!< SYSCFG peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Pos (13U) +#define RCC_MC_APB3LPENCLRR_VREFLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_VREFLPEN_Pos) /*!< 0x00002000 */ +#define RCC_MC_APB3LPENCLRR_VREFLPEN RCC_MC_APB3LPENCLRR_VREFLPEN_Msk /*!< VREF peripheral clocks enable during CSleep mode */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Pos (16U) +#define RCC_MC_APB3LPENCLRR_DTSLPEN_Msk (0x1U << RCC_MC_APB3LPENCLRR_DTSLPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_APB3LPENCLRR_DTSLPEN RCC_MC_APB3LPENCLRR_DTSLPEN_Msk /*!< DTS peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENSETR register **************/ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN RCC_MC_AHB2LPENSETR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENSETR_DMA2LPEN RCC_MC_AHB2LPENSETR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN RCC_MC_AHB2LPENSETR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENSETR_ADC12LPEN RCC_MC_AHB2LPENSETR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENSETR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENSETR_USBOLPEN RCC_MC_AHB2LPENSETR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN RCC_MC_AHB2LPENSETR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB2LPENCLRR register **************/ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos (0U) +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN RCC_MC_AHB2LPENCLRR_DMA1LPEN_Msk /*!< DMA1 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos (1U) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMA2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN RCC_MC_AHB2LPENCLRR_DMA2LPEN_Msk /*!< DMA2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos (2U) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN RCC_MC_AHB2LPENCLRR_DMAMUXLPEN_Msk /*!< DMAMUX peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos (5U) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN RCC_MC_AHB2LPENCLRR_ADC12LPEN_Msk /*!< ADC1&2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos (8U) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_USBOLPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB2LPENCLRR_USBOLPEN RCC_MC_AHB2LPENCLRR_USBOLPEN_Msk /*!< USBO peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos (16U) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk (0x1U << RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Pos) /*!< 0x00010000 */ +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN RCC_MC_AHB2LPENCLRR_SDMMC3LPEN_Msk /*!< SDMMC3 and SDMMC3 delay (DLYBSD3) block peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENSETR register **************/ +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENSETR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN RCC_MC_AHB3LPENSETR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN RCC_MC_AHB3LPENSETR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENSETR_HASH2LPEN RCC_MC_AHB3LPENSETR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENSETR_RNG2LPEN RCC_MC_AHB3LPENSETR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENSETR_CRC2LPEN RCC_MC_AHB3LPENSETR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENSETR_HSEMLPEN RCC_MC_AHB3LPENSETR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENSETR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENSETR_IPCCLPEN RCC_MC_AHB3LPENSETR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB3LPENCLRR register **************/ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos (0U) +#define RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_DCMILPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN RCC_MC_AHB3LPENCLRR_DCMILPEN_Msk /*!< DCMI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos (4U) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN RCC_MC_AHB3LPENCLRR_CRYP2LPEN_Msk /*!< CRYP2 (3DES/AES2) peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos (5U) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HASH2LPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN RCC_MC_AHB3LPENCLRR_HASH2LPEN_Msk /*!< HASH2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos (6U) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_RNG2LPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN RCC_MC_AHB3LPENCLRR_RNG2LPEN_Msk /*!< RNG2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos (7U) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_CRC2LPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN RCC_MC_AHB3LPENCLRR_CRC2LPEN_Msk /*!< CRC2 peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos (11U) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_HSEMLPEN_Pos) /*!< 0x00000800 */ +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN RCC_MC_AHB3LPENCLRR_HSEMLPEN_Msk /*!< HSEM peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos (12U) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk (0x1U << RCC_MC_AHB3LPENCLRR_IPCCLPEN_Pos) /*!< 0x00001000 */ +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN RCC_MC_AHB3LPENCLRR_IPCCLPEN_Msk /*!< IPCC peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENSETR register **************/ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN RCC_MC_AHB4LPENSETR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN RCC_MC_AHB4LPENSETR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN RCC_MC_AHB4LPENSETR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENSETR_GPIODLPEN RCC_MC_AHB4LPENSETR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENSETR_GPIOELPEN RCC_MC_AHB4LPENSETR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN RCC_MC_AHB4LPENSETR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN RCC_MC_AHB4LPENSETR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN RCC_MC_AHB4LPENSETR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENSETR_GPIOILPEN RCC_MC_AHB4LPENSETR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN RCC_MC_AHB4LPENSETR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENSETR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN RCC_MC_AHB4LPENSETR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AHB4LPENCLRR register **************/ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos (0U) +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN RCC_MC_AHB4LPENCLRR_GPIOALPEN_Msk /*!< GPIOA peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos (1U) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN RCC_MC_AHB4LPENCLRR_GPIOBLPEN_Msk /*!< GPIOB peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos (2U) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN RCC_MC_AHB4LPENCLRR_GPIOCLPEN_Msk /*!< GPIOC peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos (3U) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN RCC_MC_AHB4LPENCLRR_GPIODLPEN_Msk /*!< GPIOD peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos (4U) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN RCC_MC_AHB4LPENCLRR_GPIOELPEN_Msk /*!< GPIOE peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos (5U) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN RCC_MC_AHB4LPENCLRR_GPIOFLPEN_Msk /*!< GPIOF peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos (6U) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN RCC_MC_AHB4LPENCLRR_GPIOGLPEN_Msk /*!< GPIOG peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos (7U) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN RCC_MC_AHB4LPENCLRR_GPIOHLPEN_Msk /*!< GPIOH peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos (8U) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOILPEN_Pos) /*!< 0x00000100 */ +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN RCC_MC_AHB4LPENCLRR_GPIOILPEN_Msk /*!< GPIOI peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos (9U) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Pos) /*!< 0x00000200 */ +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN RCC_MC_AHB4LPENCLRR_GPIOJLPEN_Msk /*!< GPIOJ peripheral clocks enable during CSleep mode */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos (10U) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk (0x1U << RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Pos) /*!< 0x00000400 */ +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN RCC_MC_AHB4LPENCLRR_GPIOKLPEN_Msk /*!< GPIOK peripheral clocks enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENSETR register **************/ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN RCC_MC_AXIMLPENSETR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_AXIMLPENCLRR register **************/ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos (0U) +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk (0x1U << RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN RCC_MC_AXIMLPENCLRR_SYSRAMLPEN_Msk /*!< SYSRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENSETR register *************/ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN RCC_MC_MLAHBLPENSETR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN RCC_MC_MLAHBLPENSETR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN RCC_MC_MLAHBLPENSETR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN RCC_MC_MLAHBLPENSETR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/************* Bit definition for RCC_MC_MLAHBLPENCLRR register *************/ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos (0U) +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN RCC_MC_MLAHBLPENCLRR_SRAM1LPEN_Msk /*!< SRAM1 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos (1U) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Pos) /*!< 0x00000002 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN RCC_MC_MLAHBLPENCLRR_SRAM2LPEN_Msk /*!< SRAM2 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos (2U) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Pos) /*!< 0x00000004 */ +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN RCC_MC_MLAHBLPENCLRR_SRAM34LPEN_Msk /*!< SRAM3 and SRAM4 interface clock enable during CSleep mode */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos (4U) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk (0x1U << RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN RCC_MC_MLAHBLPENCLRR_RETRAMLPEN_Msk /*!< RETRAM interface clock enable during CSleep mode */ + +/*************** Bit definition for RCC_MC_RSTSCLRR register ****************/ +#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U) +#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */ +#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U) +#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */ +#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*!< BOR reset flag */ +#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U) +#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */ +#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*!< NRST reset flag */ +#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U) +#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */ +#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*!< HSE CSS reset flag */ +#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U) +#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */ +#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*!< VDDCORE reset flag */ +#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U) +#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000020 */ +#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*!< MCU reset flag */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U) +#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */ +#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*!< MPU System reset flag */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U) +#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */ +#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*!< MCU System reset flag */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U) +#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */ +#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*!< IWDG1 reset flag */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U) +#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */ +#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*!< IWDG2 reset flag */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U) +#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000400 */ +#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*!< WWDG1 reset flag */ + +/***************** Bit definition for RCC_MC_CIER register ******************/ +#define RCC_MC_CIER_LSIRDYIE_Pos (0U) +#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*!< LSI ready Interrupt Enable */ +#define RCC_MC_CIER_LSERDYIE_Pos (1U) +#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*!< LSE ready Interrupt Enable */ +#define RCC_MC_CIER_HSIRDYIE_Pos (2U) +#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*!< HSI ready Interrupt Enable */ +#define RCC_MC_CIER_HSERDYIE_Pos (3U) +#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*!< HSE ready Interrupt Enable */ +#define RCC_MC_CIER_CSIRDYIE_Pos (4U) +#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*!< CSI ready Interrupt Enable */ +#define RCC_MC_CIER_PLL1DYIE_Pos (8U) +#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*!< PLL1 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL2DYIE_Pos (9U) +#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*!< PLL2 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL3DYIE_Pos (10U) +#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*!< PLL3 ready Interrupt Enable */ +#define RCC_MC_CIER_PLL4DYIE_Pos (11U) +#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*!< PLL4 ready Interrupt Enable */ +#define RCC_MC_CIER_LSECSSIE_Pos (16U) +#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*!< LSE clock security system Interrupt Enable */ +#define RCC_MC_CIER_WKUPIE_Pos (20U) +#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*!< Wake up from CStop Interrupt Enable */ + +/***************** Bit definition for RCC_MC_CIFR register ******************/ +#define RCC_MC_CIFR_LSIRDYF_Pos (0U) +#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*!< LSI ready Interrupt Flag */ +#define RCC_MC_CIFR_LSERDYF_Pos (1U) +#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*!< LSE ready Interrupt Flag */ +#define RCC_MC_CIFR_HSIRDYF_Pos (2U) +#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*!< HSI ready Interrupt Flag */ +#define RCC_MC_CIFR_HSERDYF_Pos (3U) +#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*!< HSE ready Interrupt Flag */ +#define RCC_MC_CIFR_CSIRDYF_Pos (4U) +#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*!< CSI ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL1DYF_Pos (8U) +#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */ +#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*!< PLL1 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL2DYF_Pos (9U) +#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */ +#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*!< PLL2 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL3DYF_Pos (10U) +#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */ +#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*!< PLL3 ready Interrupt Flag */ +#define RCC_MC_CIFR_PLL4DYF_Pos (11U) +#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */ +#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*!< PLL4 ready Interrupt Flag */ +#define RCC_MC_CIFR_LSECSSF_Pos (16U) +#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */ +#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*!< LSE clock security system Interrupt Flag */ +#define RCC_MC_CIFR_WKUPF_Pos (20U) +#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */ +#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*!< Wake up from CStop Interrupt Flag */ + +/******************* Bit definition for RCC_VERR register *******************/ +#define RCC_VERR_MINREV_Pos (0U) +#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk /*!< Minor Revision of the IP */ +#define RCC_VERR_MINREV_0 (0x1U << RCC_VERR_MINREV_Pos) /*!< 0x00000001 */ +#define RCC_VERR_MINREV_1 (0x2U << RCC_VERR_MINREV_Pos) /*!< 0x00000002 */ +#define RCC_VERR_MINREV_2 (0x4U << RCC_VERR_MINREV_Pos) /*!< 0x00000004 */ +#define RCC_VERR_MINREV_3 (0x8U << RCC_VERR_MINREV_Pos) /*!< 0x00000008 */ +#define RCC_VERR_MAJREV_Pos (4U) +#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk /*!< Major Revision of the IP */ +#define RCC_VERR_MAJREV_0 (0x1U << RCC_VERR_MAJREV_Pos) /*!< 0x00000010 */ +#define RCC_VERR_MAJREV_1 (0x2U << RCC_VERR_MAJREV_Pos) /*!< 0x00000020 */ +#define RCC_VERR_MAJREV_2 (0x4U << RCC_VERR_MAJREV_Pos) /*!< 0x00000040 */ +#define RCC_VERR_MAJREV_3 (0x8U << RCC_VERR_MAJREV_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for RCC_IDR register ********************/ +#define RCC_IDR_ID_Pos (0U) +#define RCC_IDR_ID_Msk (0xFFFFFFFFU << RCC_IDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_IDR_ID RCC_IDR_ID_Msk /*!< Identifier of the RCC */ +#define RCC_IDR_ID_0 (0x1U << RCC_IDR_ID_Pos) /*!< 0x00000001 */ +#define RCC_IDR_ID_1 (0x2U << RCC_IDR_ID_Pos) /*!< 0x00000002 */ +#define RCC_IDR_ID_2 (0x4U << RCC_IDR_ID_Pos) /*!< 0x00000004 */ +#define RCC_IDR_ID_3 (0x8U << RCC_IDR_ID_Pos) /*!< 0x00000008 */ +#define RCC_IDR_ID_4 (0x10U << RCC_IDR_ID_Pos) /*!< 0x00000010 */ +#define RCC_IDR_ID_5 (0x20U << RCC_IDR_ID_Pos) /*!< 0x00000020 */ +#define RCC_IDR_ID_6 (0x40U << RCC_IDR_ID_Pos) /*!< 0x00000040 */ +#define RCC_IDR_ID_7 (0x80U << RCC_IDR_ID_Pos) /*!< 0x00000080 */ +#define RCC_IDR_ID_8 (0x100U << RCC_IDR_ID_Pos) /*!< 0x00000100 */ +#define RCC_IDR_ID_9 (0x200U << RCC_IDR_ID_Pos) /*!< 0x00000200 */ +#define RCC_IDR_ID_10 (0x400U << RCC_IDR_ID_Pos) /*!< 0x00000400 */ +#define RCC_IDR_ID_11 (0x800U << RCC_IDR_ID_Pos) /*!< 0x00000800 */ +#define RCC_IDR_ID_12 (0x1000U << RCC_IDR_ID_Pos) /*!< 0x00001000 */ +#define RCC_IDR_ID_13 (0x2000U << RCC_IDR_ID_Pos) /*!< 0x00002000 */ +#define RCC_IDR_ID_14 (0x4000U << RCC_IDR_ID_Pos) /*!< 0x00004000 */ +#define RCC_IDR_ID_15 (0x8000U << RCC_IDR_ID_Pos) /*!< 0x00008000 */ +#define RCC_IDR_ID_16 (0x10000U << RCC_IDR_ID_Pos) /*!< 0x00010000 */ +#define RCC_IDR_ID_17 (0x20000U << RCC_IDR_ID_Pos) /*!< 0x00020000 */ +#define RCC_IDR_ID_18 (0x40000U << RCC_IDR_ID_Pos) /*!< 0x00040000 */ +#define RCC_IDR_ID_19 (0x80000U << RCC_IDR_ID_Pos) /*!< 0x00080000 */ +#define RCC_IDR_ID_20 (0x100000U << RCC_IDR_ID_Pos) /*!< 0x00100000 */ +#define RCC_IDR_ID_21 (0x200000U << RCC_IDR_ID_Pos) /*!< 0x00200000 */ +#define RCC_IDR_ID_22 (0x400000U << RCC_IDR_ID_Pos) /*!< 0x00400000 */ +#define RCC_IDR_ID_23 (0x800000U << RCC_IDR_ID_Pos) /*!< 0x00800000 */ +#define RCC_IDR_ID_24 (0x1000000U << RCC_IDR_ID_Pos) /*!< 0x01000000 */ +#define RCC_IDR_ID_25 (0x2000000U << RCC_IDR_ID_Pos) /*!< 0x02000000 */ +#define RCC_IDR_ID_26 (0x4000000U << RCC_IDR_ID_Pos) /*!< 0x04000000 */ +#define RCC_IDR_ID_27 (0x8000000U << RCC_IDR_ID_Pos) /*!< 0x08000000 */ +#define RCC_IDR_ID_28 (0x10000000U << RCC_IDR_ID_Pos) /*!< 0x10000000 */ +#define RCC_IDR_ID_29 (0x20000000U << RCC_IDR_ID_Pos) /*!< 0x20000000 */ +#define RCC_IDR_ID_30 (0x40000000U << RCC_IDR_ID_Pos) /*!< 0x40000000 */ +#define RCC_IDR_ID_31 (0x80000000U << RCC_IDR_ID_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for RCC_SIDR register *******************/ +#define RCC_SIDR_SID_Pos (0U) +#define RCC_SIDR_SID_Msk (0xFFFFFFFFU << RCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */ +#define RCC_SIDR_SID RCC_SIDR_SID_Msk /*!< Decoding space is 4 kbytes */ +#define RCC_SIDR_SID_0 (0x1U << RCC_SIDR_SID_Pos) /*!< 0x00000001 */ +#define RCC_SIDR_SID_1 (0x2U << RCC_SIDR_SID_Pos) /*!< 0x00000002 */ +#define RCC_SIDR_SID_2 (0x4U << RCC_SIDR_SID_Pos) /*!< 0x00000004 */ +#define RCC_SIDR_SID_3 (0x8U << RCC_SIDR_SID_Pos) /*!< 0x00000008 */ +#define RCC_SIDR_SID_4 (0x10U << RCC_SIDR_SID_Pos) /*!< 0x00000010 */ +#define RCC_SIDR_SID_5 (0x20U << RCC_SIDR_SID_Pos) /*!< 0x00000020 */ +#define RCC_SIDR_SID_6 (0x40U << RCC_SIDR_SID_Pos) /*!< 0x00000040 */ +#define RCC_SIDR_SID_7 (0x80U << RCC_SIDR_SID_Pos) /*!< 0x00000080 */ +#define RCC_SIDR_SID_8 (0x100U << RCC_SIDR_SID_Pos) /*!< 0x00000100 */ +#define RCC_SIDR_SID_9 (0x200U << RCC_SIDR_SID_Pos) /*!< 0x00000200 */ +#define RCC_SIDR_SID_10 (0x400U << RCC_SIDR_SID_Pos) /*!< 0x00000400 */ +#define RCC_SIDR_SID_11 (0x800U << RCC_SIDR_SID_Pos) /*!< 0x00000800 */ +#define RCC_SIDR_SID_12 (0x1000U << RCC_SIDR_SID_Pos) /*!< 0x00001000 */ +#define RCC_SIDR_SID_13 (0x2000U << RCC_SIDR_SID_Pos) /*!< 0x00002000 */ +#define RCC_SIDR_SID_14 (0x4000U << RCC_SIDR_SID_Pos) /*!< 0x00004000 */ +#define RCC_SIDR_SID_15 (0x8000U << RCC_SIDR_SID_Pos) /*!< 0x00008000 */ +#define RCC_SIDR_SID_16 (0x10000U << RCC_SIDR_SID_Pos) /*!< 0x00010000 */ +#define RCC_SIDR_SID_17 (0x20000U << RCC_SIDR_SID_Pos) /*!< 0x00020000 */ +#define RCC_SIDR_SID_18 (0x40000U << RCC_SIDR_SID_Pos) /*!< 0x00040000 */ +#define RCC_SIDR_SID_19 (0x80000U << RCC_SIDR_SID_Pos) /*!< 0x00080000 */ +#define RCC_SIDR_SID_20 (0x100000U << RCC_SIDR_SID_Pos) /*!< 0x00100000 */ +#define RCC_SIDR_SID_21 (0x200000U << RCC_SIDR_SID_Pos) /*!< 0x00200000 */ +#define RCC_SIDR_SID_22 (0x400000U << RCC_SIDR_SID_Pos) /*!< 0x00400000 */ +#define RCC_SIDR_SID_23 (0x800000U << RCC_SIDR_SID_Pos) /*!< 0x00800000 */ +#define RCC_SIDR_SID_24 (0x1000000U << RCC_SIDR_SID_Pos) /*!< 0x01000000 */ +#define RCC_SIDR_SID_25 (0x2000000U << RCC_SIDR_SID_Pos) /*!< 0x02000000 */ +#define RCC_SIDR_SID_26 (0x4000000U << RCC_SIDR_SID_Pos) /*!< 0x04000000 */ +#define RCC_SIDR_SID_27 (0x8000000U << RCC_SIDR_SID_Pos) /*!< 0x08000000 */ +#define RCC_SIDR_SID_28 (0x10000000U << RCC_SIDR_SID_Pos) /*!< 0x10000000 */ +#define RCC_SIDR_SID_29 (0x20000000U << RCC_SIDR_SID_Pos) /*!< 0x20000000 */ +#define RCC_SIDR_SID_30 (0x40000000U << RCC_SIDR_SID_Pos) /*!< 0x40000000 */ +#define RCC_SIDR_SID_31 (0x80000000U << RCC_SIDR_SID_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ @@ -24178,7 +31473,6 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk - /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ @@ -24792,42 +32086,42 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ /******************** Bits definition for TAMP_CR2 register ***************/ -#define TAMP_CR2_TAMPNOERASE_Pos (0U) -#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ -#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMPMSK_Pos (16U) -#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ -#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_TAMPTRG_Pos (24U) -#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ -#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMPNOERASE_Pos (0U) +#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */ +#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMPMSK_Pos (16U) +#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */ +#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_TAMPTRG_Pos (24U) +#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */ +#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ @@ -24851,78 +32145,81 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMPAM_Pos (0U) -#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */ -#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <VER) +#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* TZPC VERSION ********************************/ #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) @@ -31910,7 +39247,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR) -/******************************* SYSCFG VERSION ********************************/ +/******************************* EXTI VERSION ********************************/ #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* PWR VERSION ********************************/ @@ -31956,13 +39293,13 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* RNG VERSION ********************************/ -#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER) +#define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* HASH VERSION ********************************/ -#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER) +#define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* CRYP VERSION ********************************/ -#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER) +#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DCMI VERSION ********************************/ #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR) @@ -32010,7 +39347,7 @@ peripheral. It shall be used to deallocate a peripheral from MCU */ #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DAC VERSION ********************************/ -#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER) +#define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR) /******************************* DSI VERSION ********************************/ #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h index e42480693f..ada2cc6396 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h @@ -70,7 +70,7 @@ * @brief CMSIS Device version number */ #define __STM32MP1xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_CMSIS_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html index 70a7bf7f9d..cf43d7fd4a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html @@ -163,11 +163,11 @@

License

-

V1.2.0 / 03-Feb-2020

+

V1.3.0 / 20-oct-2020

Main changes

-
  • Header files: 
    • Add new Part Number for 800MHz
    • Update license with BSD 3-Clause template
    • Rework CMSIS for RTC/TAMP, GPIO and TIM
    • Rename TIM Break source bit definition
  • Update Linker Template file for KEIL and IAR:
    • Add OpenAMP region ( region present by default, to comment if needed )

+
  • Header files: 
    • Rename  RCC bit definition to be more compliant with the name from RCC spec
    • Update STGEN register structure
    • Fix typo in MDMA register definition

Contents

@@ -181,7 +181,13 @@

Contents